From patchwork Fri Oct 14 03:17:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiufu Guo X-Patchwork-Id: 2480 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp592454wrs; Thu, 13 Oct 2022 20:18:42 -0700 (PDT) X-Google-Smtp-Source: AMsMyM72Y1583Cp0C9LNJ3ICK1b00nphp3lk1kjx6/xBPjwA91aPVASIBd6eKlxSZQ3izub8/IcZ X-Received: by 2002:a05:6402:46:b0:45c:bd68:6ab0 with SMTP id f6-20020a056402004600b0045cbd686ab0mr2439992edu.16.1665717522565; Thu, 13 Oct 2022 20:18:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665717522; cv=none; d=google.com; s=arc-20160816; b=N+eSjfgU+O+wxFkRLsTQa2RMqXB1qhUShRJGxTO/bJzTVDS3SJ4dc7i/NulWDBGkbh kOMIx/LxKzQRRFIenwCkFmvZuYnAyE8DDbsUoPZkTxEHvEJndSD3FclxTzD5zjy4QgOe eIB++y2x2gQh4Cxn5PWAZugiXOCz87yEM04sYq9AQnRqYFN51V031JMdCAhBYH/Lhbzd jrdUuVDXa7PQ7TNP+Ra4wgSaWipemvFnZlGtqgYgN0S7hsq0F66IpwGUzJON0+3Z4Q+l GWLfg9QV+txZZlr1EUef/CzgxpPEXBSZiNedEXmrbvK2JB63/LYyUQMexWTKKQ00TOWg 2Q3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mime-version:message-id:date:subject:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=iL6wnV81wHiKykcKEsGQTxOqNIIgn4r0R2086Pm51vQ=; b=buRiSsElbsLX5ftJG8OnCJPkFS7xp8CYrIx3SJdRS0lq2SJXos0JEzub3+7VcEug2u iFqf2/5SW97a8uyG3LMfOHfXK9kWhAPIqYpyMUjn7DaSBJ5np3S32bJxBqB1+q63fR/B bOMR5rauNqLJ2UcvDu5YaBIEjtCkWaqqRwVmCsEclUnAW4PThPIeotJq1Ok+aiRGY0Aj 76xjoZcjFuAGYISC0/x5pjZE5UtiLu9kgwgxVCwbzSTRR3tid0Q6yECanXX9xThIlou+ Y3RFtPdqq8EDFX/t+PJ7qdIBU5cXHLZorfcEQYRcKEyFxr9txUEb9BzedtgVq1LgwmzB Bprg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=N4wpxtY+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id c40-20020a509fab000000b0045c1708ca45si1067088edf.297.2022.10.13.20.18.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 20:18:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=N4wpxtY+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55D2E385783E for ; Fri, 14 Oct 2022 03:18:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 55D2E385783E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665717521; bh=iL6wnV81wHiKykcKEsGQTxOqNIIgn4r0R2086Pm51vQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=N4wpxtY+H2UgnUbvCj033EIoBo9Vcjkyf05uLouXJdJkN0+cens8pFcsPTuJvnhhI AgPd2tgvQAb/E8S1TTmOE3gOsFjgigywoZAbSsc4KmqfDnMuo34uG0bgFevjJ1t0H0 j3Dj7mhjlwzRTxUcSRBBSmHXKJ5vu9CKqFEEYniQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 0ED843858C39; Fri, 14 Oct 2022 03:17:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0ED843858C39 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E0Huju030130; Fri, 14 Oct 2022 03:17:55 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3k6m0k3wpp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Oct 2022 03:17:55 +0000 Received: from m0098421.ppops.net (m0098421.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 29E3Hsqh023151; Fri, 14 Oct 2022 03:17:54 GMT Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3k6m0k3wp0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Oct 2022 03:17:54 +0000 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 29E38sYI016627; Fri, 14 Oct 2022 03:17:52 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma04fra.de.ibm.com with ESMTP id 3k30u9ecvx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 14 Oct 2022 03:17:52 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 29E3HoV7655900 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 14 Oct 2022 03:17:50 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 306A35204E; Fri, 14 Oct 2022 03:17:50 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 6664B5204F; Fri, 14 Oct 2022 03:17:49 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH] rs6000: Enable const_anchor for 'addi' Date: Fri, 14 Oct 2022 11:17:48 +0800 Message-Id: <20221014031748.55813-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: aOFhSsgtpVXcSxndfK84U41M50-FEV_W X-Proofpoint-ORIG-GUID: ATiHcamsnqobnZUCwm4Y4H4R2nc_0uEQ X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-13_10,2022-10-13_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 suspectscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210140016 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jiufu Guo via Gcc-patches From: Jiufu Guo Reply-To: Jiufu Guo Cc: dje.gcc@gmail.com, segher@kernel.crashing.org, linkw@gcc.gnu.org Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746631416936100619?= X-GMAIL-MSGID: =?utf-8?q?1746631416936100619?= Hi, There is a functionality as const_anchor in cse.cc. This const_anchor supports to generate new constants through adding small gap/offsets to existing constant. For example: void __attribute__ ((noinline)) foo (long long *a) { *a++ = 0x2351847027482577LL; *a++ = 0x2351847027482578LL; } The second constant (0x2351847027482578LL) can be compated by adding '1' to the first constant (0x2351847027482577LL). This is profitable if more than one instructions are need to build the second constant. * For rs6000, we can enable this functionality, as the instruction 'addi' is just for this when gap is smaller than 0x8000. * Besides enabling TARGET_CONST_ANCHOR on rs6000, this patch also fixed one issue. The issue is: "gcc_assert (SCALAR_INT_MODE_P (mode))" is an requirement for function "try_const_anchors". e.g. it may not need to check const_anchor for {[%1:DI]=0;} which is in BLK mode. And "SCALAR_INT_MODE_P (mode)" is checked when invoking insert_const_anchors. So, this patch also adds this checking before calling try_const_anchors. * One potential side effect of this patch: Comparing with "r101=0x2351847027482577LL ... r201=0x2351847027482578LL" The new r201 will be "r201=r101+1", and then r101 will live longer, and would increase pressure when allocating registers. But I feel, this would be acceptable for this const_anchor feature. * With this patch, I checked the performance change on SPEC2017, while, and the performance is not aggressive, since this functionality is not hit on any hot path. There are runtime wavings/noise(e.g. on povray_r/xalancbmk_r/xz_r), that are not caused by the patch. With this patch, I also checked the changes in object files (from GCC bootstrap and SPEC), the significant changes are the improvement that: "addi" vs. "2 or more insns: lis+or.."; it also exposes some other optimizations opportunities: like combine/jump2. While the code to store/load one more register is also occurring in few cases, but it does not impact overall performance. * To refine this patch, some history discussions are referenced: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=33699 https://gcc.gnu.org/pipermail/gcc-patches/2009-April/260421.html https://gcc.gnu.org/pipermail/gcc-patches/2021-March/566744.html Bootstrap and regtest pass on ppc64 and ppc64le for this patch. Is this ok for trunk? BR, Jeff (Jiufu) gcc/ChangeLog: * config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define. * cse.cc (cse_insn): Add guard condition. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const_anchors.c: New test. * gcc.target/powerpc/try_const_anchors_ice.c: New test. --- gcc/config/rs6000/rs6000.cc | 4 ++++ gcc/cse.cc | 3 ++- .../gcc.target/powerpc/const_anchors.c | 20 +++++++++++++++++++ .../powerpc/try_const_anchors_ice.c | 16 +++++++++++++++ 4 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/const_anchors.c create mode 100644 gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d2743f7bce6..80cded6dec1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1760,6 +1760,10 @@ static const struct attribute_spec rs6000_attribute_table[] = #undef TARGET_UPDATE_IPA_FN_TARGET_INFO #define TARGET_UPDATE_IPA_FN_TARGET_INFO rs6000_update_ipa_fn_target_info + +#undef TARGET_CONST_ANCHOR +#define TARGET_CONST_ANCHOR 0x8000 + /* Processor table. */ diff --git a/gcc/cse.cc b/gcc/cse.cc index b13afd4ba72..56542b91c1e 100644 --- a/gcc/cse.cc +++ b/gcc/cse.cc @@ -5005,7 +5005,8 @@ cse_insn (rtx_insn *insn) if (targetm.const_anchor && !src_related && src_const - && GET_CODE (src_const) == CONST_INT) + && GET_CODE (src_const) == CONST_INT + && SCALAR_INT_MODE_P (mode)) { src_related = try_const_anchors (src_const, mode); src_related_is_const_anchor = src_related != NULL_RTX; diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c new file mode 100644 index 00000000000..39958ff9765 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target has_arch_ppc64 } } */ +/* { dg-options "-O2" } */ + +#define C1 0x2351847027482577ULL +#define C2 0x2351847027482578ULL + +void __attribute__ ((noinline)) foo (long long *a) +{ + *a++ = C1; + *a++ = C2; +} + +void __attribute__ ((noinline)) foo1 (long long *a, long long b) +{ + *a++ = C1; + if (b) + *a++ = C2; +} + +/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c new file mode 100644 index 00000000000..4c8a892e803 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* __builtin_stack_restore could generates {[%1:DI]=0;} in BLK mode, + it could case ICE in try_const_anchors which only supports SCALAR_INT. */ + +long +foo (const int val) +{ + if (val == (0)) + return 0; + void *p = __builtin_stack_save (); + char c = val; + __builtin_stack_restore (p); + return c; +}