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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n8-20020a05640205c800b00457f5aa9dc6si14512167edx.528.2022.10.10.21.49.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 21:49:06 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 620BB3857379 for ; Tue, 11 Oct 2022 04:48:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id E37523858C2D for ; Tue, 11 Oct 2022 04:48:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E37523858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1665463702t1urymcq Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 11 Oct 2022 12:48:21 +0800 (CST) X-QQ-SSF: 01400000000000D0J000000A0000000 X-QQ-FEAT: +ynUkgUhZJkpspzw5q+YXpVpoLaIgmA2eBwID6jBfvANWFmpvd7r/wkSJiM+C w4bdgDNl98mTtDDrcSfkFcCQJ4TByDpjECzVx7kd94O+WeMfIDJmoPctziB4zjeVrAvz3bk hN8DbKZu+qu8fO+BEpzDN2uaQe/q9C36NxNSKniGYLQcADASpHs4MVgGT1HvRd3+0eAsQ55 jerTIZFBOZvCgRzeAzjLGGKcL1JeJNRSHJ+f7SdPB2GLzypT0o+QtR1+mNI3vhA2lqEP0gx hEXPiK2bKQpsR8p0Tun8XIBmKUTyEV/2dp9hNacqMsGDNn1kKRXxkjAhEsgjAs8PvvH6yF9 xoYMCp5x/JQll7aUt2tytg69fGPLu/GpbuSkEYh9JE6x/V451PyZkn1oYOTJQ== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Move function place to make it looks better. Date: Tue, 11 Oct 2022 12:48:20 +0800 Message-Id: <20221011044820.312228-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746365313944052180?= X-GMAIL-MSGID: =?utf-8?q?1746365313944052180?= From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher): Move down like ARM SVE. (rvv_switcher::~rvv_switcher): Move down like ARM SVE. (mangle_builtin_type): Move down to make it together with other global function. (class rvv_switcher): Move from riscv-vector-builtins.h. * config/riscv/riscv-vector-builtins.h (class rvv_switcher): Move to riscv-vector-builtins.cc. --- gcc/config/riscv/riscv-vector-builtins.cc | 79 ++++++++++++++--------- gcc/config/riscv/riscv-vector-builtins.h | 19 ------ 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 7033b1fc176..6fd1bb0fcb2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -86,23 +86,6 @@ static GTY(()) tree abi_vector_types[NUM_VECTOR_TYPES + 1]; extern GTY(()) tree builtin_vector_types[MAX_TUPLE_SIZE][NUM_VECTOR_TYPES + 1]; tree builtin_vector_types[MAX_TUPLE_SIZE][NUM_VECTOR_TYPES + 1]; -rvv_switcher::rvv_switcher () -{ - /* Set have_regs_of_mode before targetm.init_builtins (). */ - memcpy (m_old_have_regs_of_mode, have_regs_of_mode, - sizeof (have_regs_of_mode)); - for (int i = 0; i < NUM_MACHINE_MODES; ++i) - if (riscv_v_ext_enabled_vector_mode_p ((machine_mode) i)) - have_regs_of_mode[i] = true; -} - -rvv_switcher::~rvv_switcher () -{ - /* Recover back have_regs_of_mode. */ - memcpy (have_regs_of_mode, m_old_have_regs_of_mode, - sizeof (have_regs_of_mode)); -} - /* Add type attributes to builtin type tree, currently only the mangled name. */ static void add_vector_type_attribute (tree type, const char *mangled_name) @@ -140,19 +123,6 @@ lookup_vector_type_attribute (const_tree type) return lookup_attribute ("RVV type", TYPE_ATTRIBUTES (type)); } -/* If TYPE is a built-in type defined by the RVV ABI, return the mangled name, - otherwise return NULL. */ -const char * -mangle_builtin_type (const_tree type) -{ - if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL) - type = TREE_TYPE (TYPE_NAME (type)); - if (tree attr = lookup_vector_type_attribute (type)) - if (tree id = TREE_VALUE (chain_index (0, TREE_VALUE (attr)))) - return IDENTIFIER_POINTER (id); - return NULL; -} - /* Register the built-in RVV ABI types, such as __rvv_int32m1_t. */ static void register_builtin_types () @@ -231,6 +201,55 @@ register_vector_type (vector_type_index type) builtin_vector_types[0][type] = vectype; } +/* RAII class for enabling enough RVV features to define the built-in + types and implement the riscv_vector.h pragma. + + Note: According to 'TYPE_MODE' macro implementation, we need set + have_regs_of_mode[mode] to be true if we want to get the exact mode + from 'TYPE_MODE'. However, have_regs_of_mode has not been set yet in + targetm.init_builtins (). We need rvv_switcher to set have_regs_of_mode + before targetm.init_builtins () and recover back have_regs_of_mode + after targetm.init_builtins (). */ +class rvv_switcher +{ +public: + rvv_switcher (); + ~rvv_switcher (); + +private: + bool m_old_have_regs_of_mode[MAX_MACHINE_MODE]; +}; + +rvv_switcher::rvv_switcher () +{ + /* Set have_regs_of_mode before targetm.init_builtins (). */ + memcpy (m_old_have_regs_of_mode, have_regs_of_mode, + sizeof (have_regs_of_mode)); + for (int i = 0; i < NUM_MACHINE_MODES; ++i) + if (riscv_v_ext_enabled_vector_mode_p ((machine_mode) i)) + have_regs_of_mode[i] = true; +} + +rvv_switcher::~rvv_switcher () +{ + /* Recover back have_regs_of_mode. */ + memcpy (have_regs_of_mode, m_old_have_regs_of_mode, + sizeof (have_regs_of_mode)); +} + +/* If TYPE is a built-in type defined by the RVV ABI, return the mangled name, + otherwise return NULL. */ +const char * +mangle_builtin_type (const_tree type) +{ + if (TYPE_NAME (type) && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL) + type = TREE_TYPE (TYPE_NAME (type)); + if (tree attr = lookup_vector_type_attribute (type)) + if (tree id = TREE_VALUE (chain_index (0, TREE_VALUE (attr)))) + return IDENTIFIER_POINTER (id); + return NULL; +} + /* Initialize all compiler built-ins related to RVV that should be defined at start-up. */ void diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index ec85e0b1320..5c01a760657 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -36,25 +36,6 @@ enum vector_type_index NUM_VECTOR_TYPES }; -/* RAII class for enabling enough RVV features to define the built-in - types and implement the riscv_vector.h pragma. - - Note: According to 'TYPE_MODE' macro implementation, we need set - have_regs_of_mode[mode] to be true if we want to get the exact mode - from 'TYPE_MODE'. However, have_regs_of_mode has not been set yet in - targetm.init_builtins (). We need rvv_switcher to set have_regs_of_mode - before targetm.init_builtins () and recover back have_regs_of_mode - after targetm.init_builtins (). */ -class rvv_switcher -{ -public: - rvv_switcher (); - ~rvv_switcher (); - -private: - bool m_old_have_regs_of_mode[MAX_MACHINE_MODE]; -}; - } // end namespace riscv_vector #endif