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[8.43.85.97]) by mx.google.com with ESMTPS id dm3-20020a170907948300b0078d3a35e181si9446392ejc.871.2022.10.10.00.30.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 00:30:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=PHkANEF1; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 439B43860750 for ; Mon, 10 Oct 2022 07:29:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 439B43860750 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665386989; bh=DOpRE1zwbNrSQyQnf7mIy0lWxwIACcIc406RsKXor2w=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=PHkANEF17STYrNeFEu7HAAau0+r1IPeYH6CK5ds+ejEA4JkUGfaghDby/JkjPMPUs /Rk07p994YiIBGQmGSJnP4y2XFfVyuTY53izKDYwThem4+l4Ax1ESqdmD/hw6lEVRg ZyfOioh3tnrEIqiFv5OSaEi0yO/vK1QF4zGB48CU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 0C3C33858438 for ; Mon, 10 Oct 2022 07:29:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0C3C33858438 Received: by mail-ej1-x629.google.com with SMTP id d26so15900685eje.10 for ; Mon, 10 Oct 2022 00:29:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=DOpRE1zwbNrSQyQnf7mIy0lWxwIACcIc406RsKXor2w=; b=byh6SulHf9TNIHiKuEN+TtdnAO9T098cxCNjybJe5C9Y1nhc7JB7ktRinpZJAXF8Cv MGfXi6dKwZlq0RMBOgSWOxgqCktNxH0CSnr/Ecxd0NGrEai/fce9uLFGAd/VZebLnrex bPiPAH9XR8zrYI1UjdP/C1517VnQXKaT2jQhEZtxDCnJ2eppc1UXHSMlYy+NHOgAc8tU 1y/5AmznV4bod6311oVY4iRt6eEQM3GLxl90oLXo+WXik5ag1JzSYCcU0e46ezlRr/K+ 6ydX/RNog6SWysT61/v+G1T9JuoSyCyL2lgXtoJp+sLt3ZdZe7Z6FezJxYQ1Os6KzAvp rumw== X-Gm-Message-State: ACrzQf11r7931zjitpBQMit0ghaI9Uwa9ZYyLWU6lETvhlQXJ7UF2laM agfHgoPOMNChBIw5339XS9nH5fY8VAM= X-Received: by 2002:a17:907:31ca:b0:780:2170:e08c with SMTP id xf10-20020a17090731ca00b007802170e08cmr13709446ejb.145.1665386944332; Mon, 10 Oct 2022 00:29:04 -0700 (PDT) Received: from fatty.nomansland ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id j1-20020a17090623e100b007317f017e64sm4901913ejg.134.2022.10.10.00.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 00:29:04 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [committed 1/5] arc: Fix enter pattern instruction's offsets Date: Mon, 10 Oct 2022 10:28:58 +0300 Message-Id: <20221010072902.3669746-1-claziss@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Claudiu Zissulescu via Gcc-patches From: Claudiu Zissulescu Ianculescu Reply-To: Claudiu Zissulescu Cc: fbedard@synopsys.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746284853247689107?= X-GMAIL-MSGID: =?utf-8?q?1746284853247689107?= The enter pattern instruction contains the necessary information for the dwarf machinery to generate the appropriate dwarf code. This patch is fixing the register offsets related to CFA, and adds a test. gcc/ * config/arc/arc.cc (arc_save_callee_enter): Use negative offsets. gcc/testsuite * gcc.target/arc/enter-dw2-1.c: New file. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.cc | 6 ++--- gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 28 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/enter-dw2-1.c diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index db4b56b23ff..7be27e01035 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -3356,7 +3356,7 @@ arc_save_callee_enter (uint64_t gmask, reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx, - off)); + -off)); XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg); RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1; off -= UNITS_PER_WORD; @@ -3370,7 +3370,7 @@ arc_save_callee_enter (uint64_t gmask, reg = gen_rtx_REG (SImode, regno); mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx, - off)); + -off)); XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg); RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx)) = 1; gmask = gmask & ~(1ULL << regno); @@ -3380,7 +3380,7 @@ arc_save_callee_enter (uint64_t gmask, { mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx, - off)); + -off)); XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, hard_frame_pointer_rtx); RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1; off -= UNITS_PER_WORD; diff --git a/gcc/testsuite/gcc.target/arc/enter-dw2-1.c b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c new file mode 100644 index 00000000000..25d03562198 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c @@ -0,0 +1,28 @@ +/* Verify that we generate appropriate CFI offsets in the case of enter + instruction. */ +/* { dg-skip-if "Not having enter_s insn." { arc700 || arc6xx } } */ +/* { dg-do compile } */ +/* { dg-options "-g -Os" } */ + +extern void bar (void); + +void foo (void) +{ + asm volatile (";my clobber list" + : : : "r13", "r14", "r15", "r16", "r17", "r18", "r19"); + bar (); + asm volatile (";my clobber list" + : : : "r13", "r14", "r15", "r16", "r17", "r18", "r19"); +} + + +/* { dg-final { scan-assembler-times "enter_s" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_def_cfa_offset 32" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 31, -32" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 13, -28" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 14, -24" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 15, -20" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 16, -16" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 17, -12" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 18, -8" 1 } } */ +/* { dg-final { scan-assembler-times "\.cfi_offset 19, -4" 1 } } */