diff mbox series

[committed,1/5] arc: Fix enter pattern instruction's offsets

Message ID 20221010072902.3669746-1-claziss@gmail.com
State New, archived
Headers
Series [committed,1/5] arc: Fix enter pattern instruction's offsets |

Commit Message

Claudiu Zissulescu Ianculescu Oct. 10, 2022, 7:28 a.m. UTC 
  The enter pattern instruction contains the necessary information for
the dwarf machinery to generate the appropriate dwarf code.  This
patch is fixing the register offsets related to CFA, and adds a test.

gcc/
	* config/arc/arc.cc (arc_save_callee_enter): Use negative offsets.

gcc/testsuite
	* gcc.target/arc/enter-dw2-1.c: New file.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
---
 gcc/config/arc/arc.cc                      |  6 ++---
 gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 28 ++++++++++++++++++++++
 2 files changed, 31 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/enter-dw2-1.c
diff mbox series

Patch

diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index db4b56b23ff..7be27e01035 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -3356,7 +3356,7 @@  arc_save_callee_enter (uint64_t gmask,
       reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
       mem = gen_frame_mem (Pmode, plus_constant (Pmode,
 						 stack_pointer_rtx,
-						 off));
+						 -off));
       XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg);
       RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1;
       off -= UNITS_PER_WORD;
@@ -3370,7 +3370,7 @@  arc_save_callee_enter (uint64_t gmask,
       reg = gen_rtx_REG (SImode, regno);
       mem = gen_frame_mem (SImode, plus_constant (Pmode,
 						  stack_pointer_rtx,
-						  off));
+						  -off));
       XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg);
       RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx)) = 1;
       gmask = gmask & ~(1ULL << regno);
@@ -3380,7 +3380,7 @@  arc_save_callee_enter (uint64_t gmask,
     {
       mem = gen_frame_mem (Pmode, plus_constant (Pmode,
 						 stack_pointer_rtx,
-						 off));
+						 -off));
       XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, hard_frame_pointer_rtx);
       RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1;
       off -= UNITS_PER_WORD;
diff --git a/gcc/testsuite/gcc.target/arc/enter-dw2-1.c b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
new file mode 100644
index 00000000000..25d03562198
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
@@ -0,0 +1,28 @@ 
+/* Verify that we generate appropriate CFI offsets in the case of enter
+   instruction.  */
+/* { dg-skip-if "Not having enter_s insn." { arc700 || arc6xx } } */
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+extern void bar (void);
+
+void foo (void)
+{
+  asm volatile (";my clobber list"
+		: : : "r13", "r14", "r15", "r16", "r17", "r18", "r19");
+  bar ();
+  asm volatile (";my clobber list"
+		: : : "r13", "r14", "r15", "r16", "r17", "r18", "r19");
+}
+
+
+/* { dg-final { scan-assembler-times "enter_s" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_def_cfa_offset 32" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 31, -32" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 13, -28" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 14, -24" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 15, -20" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 16, -16" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 17, -12" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 18, -8" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 19, -4" 1 } } */