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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f11-20020a0564021e8b00b0044e6e3302cesi11226911edf.469.2022.09.13.02.37.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Sep 2022 02:37:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4AD2938A284F for ; Tue, 13 Sep 2022 09:37:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id BA740389EC3D for ; Tue, 13 Sep 2022 09:36:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BA740389EC3D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowAAHaA0eTyBjFWg0Ag--.35371S2; Tue, 13 Sep 2022 17:36:31 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc. Date: Tue, 13 Sep 2022 17:36:16 +0800 Message-Id: <20220913093616.1422179-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowAAHaA0eTyBjFWg0Ag--.35371S2 X-Coremail-Antispam: 1UD129KBjvJXoWxCr48Kr1rCFWUAFyrtr4rGrg_yoWrXrW7pa 98Gw4Svr95GFs2grsrtFWfWayrtwn3Kr43Aw4UAr4UCw4DZry8AFn3Kw43ZrnrXan8A347 ZF1F9Fyakw4UCa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUka14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE174l42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWrJr0_WFyUJwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY 6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JU8rcfUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgAIAGKY1r1gyQAAs6 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiawei , wuwei2016@iscas.ac.cn, kito.cheng@sifive.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1743846725609809780?= X-GMAIL-MSGID: =?utf-8?q?1743846725609809780?= From: Jiawei Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, it will add csr-check in .option section and pass this to assembler. V2: Add assembler support check info for -mcsr-check. Thanks for Kito's suggestions. gcc/ChangeLog: * config.in: New def. * config/riscv/riscv.cc (riscv_file_start): New .option. * config/riscv/riscv.opt: New options. * configure.ac: New check. * doc/invoke.texi: New def. --- gcc/config.in | 6 ++++++ gcc/config/riscv/riscv.cc | 5 +++++ gcc/config/riscv/riscv.opt | 6 ++++++ gcc/configure.ac | 5 +++++ gcc/doc/invoke.texi | 6 ++++++ 5 files changed, 28 insertions(+) diff --git a/gcc/config.in b/gcc/config.in index 9c53319b544..a4c39e1384d 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -616,6 +616,12 @@ #endif +/* Define if your assembler supports -mcsr-check. */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_MCSR_CHECK +#endif + + /* Define if your Mac OS X assembler supports -mllvm -x86-pad-for-align=false. */ #ifndef USED_FOR_TARGET diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 675d92c0961..e98e6b1f561 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5135,6 +5135,11 @@ riscv_file_start (void) if (! riscv_mrelax) fprintf (asm_out_file, "\t.option norelax\n"); + /* If the user specifies "-mcsr-check" on the command line then enable csr + check in the assembler. */ + if (riscv_mcsr_check) + fprintf (asm_out_file, "\t.option csr-check\n"); + if (riscv_emit_attribute_p) riscv_emit_attribute (); } diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index fbca91b956c..3a12dd47310 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. +mcsr-check +Target Bool Var(riscv_mcsr_check) Init(1) +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. + Mask(64BIT) Mask(MUL) diff --git a/gcc/configure.ac b/gcc/configure.ac index 50bb61c1b61..1a9288ee659 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5269,6 +5269,11 @@ configured with --enable-newlib-nano-formatted-io.]) [-march=rv32i_zifencei2p0],,, [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1, [Define if the assembler understands -march=rv*_zifencei.])]) + gcc_GAS_CHECK_FEATURE([-mcsr-check], + gcc_cv_as_riscv_csr_check, + [-mcsr-check],,, + [AC_DEFINE(HAVE_AS_MCSR_CHECK, 1, + [Define if the assembler understands -mcsr-check.])]) ;; loongarch*-*-*) gcc_GAS_CHECK_FEATURE([.dtprelword support], diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index dd3302fcd15..7caade26b94 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options. -mbig-endian -mlittle-endian @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol -mstack-protector-guard-offset=@var{offset}} +-mcsr-check -mno-csr-check @gol @emph{RL78 Options} @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol @@ -28551,6 +28552,11 @@ linker relaxations. Emit (do not emit) RISC-V attribute to record extra information into ELF objects. This feature requires at least binutils 2.32. +@item -mcsr-check +@itemx -mno-csr-check +@opindex mcsr-check +Enables or disables the CSR checking. + @item -malign-data=@var{type} @opindex malign-data Control how GCC aligns variables and constants of array, structure, or union