RISC-V: Fix annotation

Message ID 20220830025742.178055-1-juzhe.zhong@rivai.ai
State New, archived
Headers
Series RISC-V: Fix annotation |

Commit Message

juzhe.zhong@rivai.ai Aug. 30, 2022, 2:57 a.m. UTC
  From: zhongjuzhe <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv.h (enum reg_class): Change vype to vtype.

---
 gcc/config/riscv/riscv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Kito Cheng Sept. 1, 2022, 2:05 a.m. UTC | #1
Thanks, pushed to trunk.

On Tue, Aug 30, 2022 at 10:58 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: zhongjuzhe <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.h (enum reg_class): Change vype to vtype.
>
> ---
>  gcc/config/riscv/riscv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 29582f7c545..3ee5a93ce6a 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -462,7 +462,7 @@ enum reg_class
>    FP_REGS,                     /* floating-point registers */
>    FRAME_REGS,                  /* arg pointer and frame pointer */
>    VL_REGS,                     /* vl register */
> -  VTYPE_REGS,                  /* vype register */
> +  VTYPE_REGS,                  /* vtype register */
>    VM_REGS,                     /* v0.t registers */
>    VD_REGS,                     /* vector registers except v0.t */
>    V_REGS,                      /* vector registers */
> --
> 2.36.1
>
  

Patch

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 29582f7c545..3ee5a93ce6a 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -462,7 +462,7 @@  enum reg_class
   FP_REGS,			/* floating-point registers */
   FRAME_REGS,			/* arg pointer and frame pointer */
   VL_REGS,			/* vl register */
-  VTYPE_REGS,			/* vype register */
+  VTYPE_REGS,			/* vtype register */
   VM_REGS,			/* v0.t registers */
   VD_REGS,			/* vector registers except v0.t */
   V_REGS,			/* vector registers */