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[8.43.85.97]) by mx.google.com with ESMTPS id hp27-20020a1709073e1b00b0073da8185a4esi8821310ejc.511.2022.08.29.18.51.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 18:51:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0BB8F382D111 for ; Tue, 30 Aug 2022 01:51:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 3F0B43830952 for ; Tue, 30 Aug 2022 01:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3F0B43830952 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp88t1661824228t06beggg Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Aug 2022 09:50:26 +0800 (CST) X-QQ-SSF: 01400000000000C0I000000A0000000 X-QQ-FEAT: pMHwdq3i9JPLKaPa7dBxlrsAc4IEN85y3/v8bT1GhZwt1tqbq6m1wa6TasASb iNSB0rTvVrUH8pQBAG4qo8GAn0Ln83FnrNDTuIknA5VxDFwJXd18sc7gbJrffsfjrxEG+63 kFrpOwOFds8NpggHm6r+wn8UgvzS8rCIwDH1329nn6zQl5XfeYwUn+AnRS4tlPcyqlC6pER njyba8U52hjsGkt67hVLFsLI8jgyeAW/xoS/XhlJG9cv9JqZrUHH2rg6xAHuRIf4jAtwqJr H1qbAAtDfampoKpFtKY4kuKwQvZOQatcTUX13+gbU9c+fadM3ZwaIWfqLDtDcgkAhXGa6yt UG53f/3qKNSFVvX9aRc1JimRSKwxUd4pT5jxDf2yFSfbrBZzYNZmkRLBfhkaQ== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Fix riscv_vector_chunks configuration according to TARGET_MIN_VLEN Date: Tue, 30 Aug 2022 09:50:24 +0800 Message-Id: <20220830015024.17543-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, zhongjuzhe Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1742549065284144186?= X-GMAIL-MSGID: =?utf-8?q?1742549065284144186?= From: zhongjuzhe gcc/ChangeLog: * config/riscv/riscv.cc (riscv_convert_vector_bits): Change configuration according to TARGET_MIN_VLEN. * config/riscv/riscv.h (UNITS_PER_FP_REG): Fix annotation. --- gcc/config/riscv/riscv.cc | 11 ++++++----- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4d439e15392..ef606f33983 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5219,14 +5219,15 @@ riscv_init_machine_status (void) static poly_uint16 riscv_convert_vector_bits (void) { - /* The runtime invariant is only meaningful when vector is enabled. */ + /* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */ if (!TARGET_VECTOR) return 0; - if (TARGET_VECTOR_ELEN_64 || TARGET_VECTOR_ELEN_FP_64) + if (TARGET_MIN_VLEN > 32) { - /* When targetting Zve64* (ELEN = 64) extensions, we should use 64-bit - chunk size. Runtime invariant: The single indeterminate represent the + /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. + Otherwise we can not include sew = 64bits. + Runtime invariant: The single indeterminate represent the number of 64-bit chunks in a vector beyond minimum length of 64 bits. Thus the number of bytes in a vector is 8 + 8 * x1 which is riscv_vector_chunks * 8 = poly_int (8, 8). */ @@ -5234,7 +5235,7 @@ riscv_convert_vector_bits (void) } else { - /* When targetting Zve32* (ELEN = 32) extensions, we should use 32-bit + /* When targetting minimum VLEN = 32, we should use 32-bit chunk size. Runtime invariant: The single indeterminate represent the number of 32-bit chunks in a vector beyond minimum length of 32 bits. Thus the number of bytes in a vector is 4 + 4 * x1 which is diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1d8139c2c9b..29582f7c545 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -160,7 +160,7 @@ ASM_MISA_SPEC /* The `Q' extension is not yet supported. */ #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) -/* Size per vector register. For zve32*, size = poly (4, 4). Otherwise, size = poly (8, 8). */ +/* Size per vector register. For VLEN = 32, size = poly (4, 4). Otherwise, size = poly (8, 8). */ #define UNITS_PER_V_REG (riscv_vector_chunks * riscv_bytes_per_vector_chunk) /* The largest type that can be passed in floating-point registers. */