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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gb11-20020a170907960b00b0074157a46cd5si402801ejc.172.2022.08.27.03.58.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Aug 2022 03:58:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7B42D388DD17 for ; Sat, 27 Aug 2022 10:58:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 38F823887F57 for ; Sat, 27 Aug 2022 10:57:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 38F823887F57 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp75t1661597855tsvmphqo Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 27 Aug 2022 18:57:34 +0800 (CST) X-QQ-SSF: 01400000002000C0I000B00A0000000 X-QQ-FEAT: 0laiA9+vjADEM3xaax1/kx2BhNhRLxndGQTUjMoFHXjo5fK9lHDcCyXGxgGmT OCDyCs4y2hTh7KJaFdEIihgeP5A1zIhAWfYT8vEzURSQAgT6YRgZ/pYnSTmdMI7zvvRa3/w Ts/s62HRa9uQDxlhLAnxPApEw7Y9EMUyZ79vmhakVgAfoR8kBUtoK9ijYVvwX8IvXx3LnMM jwO3BIbKPokKmcyALYIraSAybrWu3VKasoGfBPG1/z7t5BVKkvGJ+QPJ5IPJOIa0Fdfl5wM YZto/hUQSuww5GKMKx/vvG86/0ngfK0NalFZLb3EMhyKbjwX3J/+pzjoyTgaROIXguAIFcP nyZRbMDafvxuOSTFrz2h/SuEVbB+JOb02x/DMw38frq2FVZT4+E55KTKQa9rWSUvLYNDN4G X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add RVV instructions classification Date: Sat, 27 Aug 2022 18:57:23 +0800 Message-Id: <20220827105723.303520-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, zhongjuzhe Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1742311712250944166?= X-GMAIL-MSGID: =?utf-8?q?1742311712250944166?= From: zhongjuzhe gcc/ChangeLog: * config/riscv/riscv.md: Add new type for vector instructions. --- gcc/config/riscv/riscv.md | 100 +++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 30cd07dc6f5..ee3e7c53b78 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -195,10 +195,108 @@ ;; nop no operation ;; ghost an instruction that produces no real code ;; bitmanip bit manipulation instructions +;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. +;; rdvlenb vector byte length vlenb csrr read +;; rdvl vector length vl csrr read +;; 7. Vector Loads and Stores +;; vlde vector unit-stride load instructions +;; vste vector unit-stride store instructions +;; vldm vector unit-stride mask load instructions +;; vstm vector unit-stride mask store instructions +;; vlds vector strided load instructions +;; vsts vector strided store instructions +;; vldux vector unordered indexed load instructions +;; vldox vector ordered indexed load instructions +;; vstux vector unordered indexed store instructions +;; vstox vector ordered indexed store instructions +;; vldff vector unit-stride fault-only-first load instructions +;; vldr vector whole register load instructions +;; vstr vector whole register store instructions +;; 11. Vector integer arithmetic instructions +;; vialu vector single-width integer add and subtract and logical nstructions +;; viwalu vector widening integer add/subtract +;; vext vector integer extension +;; vicalu vector arithmetic with carry or borrow instructions +;; vshift vector single-width bit shift instructions +;; vnshift vector narrowing integer shift instructions +;; vicmp vector integer comparison/min/max instructions +;; vimul vector single-width integer multiply instructions +;; vidiv vector single-width integer divide instructions +;; viwmul vector widening integer multiply instructions +;; vimuladd vector single-width integer multiply-add instructions +;; viwmuladd vector widening integer multiply-add instructions +;; vimerge vector integer merge instructions +;; vimov vector integer move vector instructions +;; 12. Vector fixed-point arithmetic instructions +;; vsalu vector single-width saturating add and subtract and logical instructions +;; vaalu vector single-width averaging add and subtract and logical instructions +;; vsmul vector single-width fractional multiply with rounding and saturation instructions +;; vsshift vector single-width scaling shift instructions +;; vnclip vector narrowing fixed-point clip instructions +;; 13. Vector floating-point instructions +;; vfalu vector single-width floating-point add/subtract instructions +;; vfwalu vector widening floating-point add/subtract instructions +;; vfmul vector single-width floating-point multiply instructions +;; vfdiv vector single-width floating-point divide instructions +;; vfwmul vector widening floating-point multiply instructions +;; vfmuladd vector single-width floating-point multiply-add instructions +;; vfwmuladd vector widening floating-point multiply-add instructions +;; vfsqrt vector floating-point square-root instructions +;; vfrecp vector floating-point reciprocal square-root instructions +;; vfcmp vector floating-point comparison/min/max instructions +;; vfsgnj vector floating-point sign-injection instructions +;; vfclass vector floating-point classify instruction +;; vfmerge vector floating-point merge instruction +;; vfmov vector floating-point move instruction +;; vfcvtitof vector single-width integer to floating-point instruction +;; vfcvtftoi vector single-width floating-point to integer instruction +;; vfwcvtitof vector widening integer to floating-point instruction +;; vfwcvtftoi vector widening floating-point to integer instruction +;; vfwcvtftof vector widening floating-point to floating-point instruction +;; vfncvtitof vector narrowing integer to floating-point instruction +;; vfncvtftoi vector narrowing floating-point to integer instruction +;; vfncvtftof vector narrowing floating-point to floating-point instruction +;; 14. Vector reduction operations +;; vired vector single-width integer reduction instructions +;; viwred vector widening integer reduction instructions +;; vfred vector single-width floating-point un-ordered reduction instruction +;; vfredo vector single-width floating-point ordered reduction instruction +;; vfwred vector widening floating-point un-ordered reduction instruction +;; vfwredo vector widening floating-point ordered reduction instruction +;; 15. Vector mask instructions +;; vmalu vector mask-register logical instructions +;; vmpop vector mask population count +;; vmffs vector find-first-set mask bit +;; vmsfs vector set mask bit +;; vmiota vector iota +;; vmidx vector element index instruction +;; 16. Vector permutation instructions +;; vimovvx integer scalar move instructions +;; vimovxv integer scalar move instructions +;; vfmovvf floating-point scalar move instructions +;; vfmovfv floating-point scalar move instructions +;; vislide vector slide instructions +;; vislide1 vector slide instructions +;; vfslide1 vector slide instructions +;; vgather vector register gather instructions +;; vcompress vector compress instruction +;; vmov whole vector register move (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate" + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, + rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts, + vldux,vldox,vstux,vstox,vldff,vldr,vstr, + vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, + vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, + vsalu,vaalu,vsmul,vsshift,vnclip, + vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp, + vfcmp,vfsgnj,vfclass,vfmerge,vfmov, + vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi, + vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof, + vired,viwred,vfred,vfredo,vfwred,vfwredo, + vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, + vislide,vislide1,vfslide1,vgather,vcompress,vmov" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions,