From patchwork Thu Jul 14 05:33:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 247 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a98:d5ce:0:b0:178:cc93:bf7d with SMTP id g14csp154168eik; Wed, 13 Jul 2022 22:34:42 -0700 (PDT) X-Google-Smtp-Source: AGRyM1sILBbGGUmJ9uTLxNvgqahCbOIVKLjME6ohAL4L368/Ty7QoVjeeBY1g+2tQKON8AyJXZYb X-Received: by 2002:a17:907:2cd4:b0:72b:7fa8:eafc with SMTP id hg20-20020a1709072cd400b0072b7fa8eafcmr7060709ejc.438.1657776882122; Wed, 13 Jul 2022 22:34:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1657776882; cv=none; d=google.com; s=arc-20160816; b=B8upOW8vrlt8AUoMChySk/LzMhqb4cnAOaipF4jV0OTxfZ8SOj9bA/TdCHP3JnwVsN a/RsjY3HRg6W2vHPIpsXZwCJh0gdIcC4B9kSj9i4/YOS/lgz4Fu7MZX8Wf9ZB0wimDNB v0O/N7KFdMLm1jUlSgHFdYJtgs1KTvCU30+robqODfmajmhbJWrruuJCgNC+wwSAhIxF ICeuOBh66fvIM9tPrHVCdblzYMCmPzkSg0jn1vLWBK9enX/jctysrP4f1HZ/348gaBoK ADUwu5BxAJuSbV8/IR2hTJBGveT7rywZ4Z+AeV7a7D2zVQeE6p503YjLYcEWzUbSeMz2 0t9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=b1ceCnelppSxrP1yg890s3XHmDlUcEmoXaH7PUdBtSU=; b=vMdonRqdFeg8J+ehsai4NHfcvXl795ah+cqsUJFTLucI/Cg/DInUtTvyxwkgrmpiwB /8ALTcCHoco8Xv6SMtl/gV88W7o6rC9QFwCAFQ7gG9Q7bG7ZN2fL6QLPMQRLnLG4UxvR F6fXba/Ubm97smdRLjaCe9lN2a/TRq/KgkLinomzxMz8PXSLQ4Yhf65j78uo84UabMr4 GVdtPknSE1h2HBxPpwrgw8F7vxaJ13oSqRu6AlP6oc0kPT2arqZHkGN2mEd6ngnUuV7W FDgxxW5IcNEMx3FfPq0k8QgqjnbaXVy25NtOf8/90sEoVym6NZdzRXCiiPLYuV1C1pNi Z07g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yLDpvd7P; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c13-20020a05640227cd00b0043a7080a79csi1175545ede.508.2022.07.13.22.34.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Jul 2022 22:34:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yLDpvd7P; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C8CC9384F021 for ; Thu, 14 Jul 2022 05:34:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C8CC9384F021 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1657776880; bh=b1ceCnelppSxrP1yg890s3XHmDlUcEmoXaH7PUdBtSU=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=yLDpvd7PIxT5CBPAOt3NhsjwM/f0RyCGb1NTd+1Dgska1OD+YmpULtWoQgxx0LHgM wRO+6S/j767qfpWWCjkLzLrRcsW/OFezQPtIvSkg2IvDyYztOsae5k1K1AONyqq4qc cJ9TztDT0RIa68BZ5PMo6aA8jcJBP1AiOcto3Lmg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 7BFA83857BB2 for ; Thu, 14 Jul 2022 05:33:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7BFA83857BB2 X-IronPort-AV: E=McAfee;i="6400,9594,10407"; a="286559515" X-IronPort-AV: E=Sophos;i="5.92,269,1650956400"; d="scan'208";a="286559515" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2022 22:33:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,269,1650956400"; d="scan'208";a="685444047" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by FMSMGA003.fm.intel.com with ESMTP; 13 Jul 2022 22:33:52 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 082E210056A8; Thu, 14 Jul 2022 13:33:52 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] Extend 64-bit vector bit_op patterns with ?r alternative Date: Thu, 14 Jul 2022 13:33:51 +0800 Message-Id: <20220714053351.7073-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: References: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1738305051610268885?= X-GMAIL-MSGID: =?utf-8?q?1738305051610268885?= And split it to GPR-version instruction after reload. > ?r was introduced under the assumption that we want vector values > mostly in vector registers. Currently there are no instructions with > memory or immediate operand, so that made sense at the time. Let's > keep ?r until logic instructions with mem/imm operands are introduced. > So, for the patch that adds 64-bit vector logic in GPR, I would advise > to first introduce only register operands. mem/imm operands should be Update patch to add ?r to 64-bit bit_op patterns. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. No big imact on SPEC2017(Most same binary). Ok for trunk? gcc/ChangeLog: PR target/106038 * config/i386/mmx.md (3): Expand with (clobber (reg:CC flags_reg)) under TARGET_64BIT (mmx_code>3): Ditto. (*mmx_3_gpr): New define_insn, add post_reload splitter after it. (mmx_andnot3_gpr): Ditto. (3): Extend follow define_split from VI_16_32 to VI_16_32_64. (*andnot3): Ditto. (mmxinsnmode): New mode attribute. (VI_16_32_64): New mode iterator. (*mov_imm): Refactor with mmxinsnmode. * config/i386/predicates.md gcc/testsuite/ChangeLog: * gcc.target/i386/pr106038-1.c: New test. * gcc.target/i386/pr106038-2.c: New test. * gcc.target/i386/pr106038-3.c: New test. --- gcc/config/i386/mmx.md | 131 +++++++++++++++------ gcc/testsuite/gcc.target/i386/pr106038-1.c | 61 ++++++++++ gcc/testsuite/gcc.target/i386/pr106038-2.c | 35 ++++++ gcc/testsuite/gcc.target/i386/pr106038-3.c | 17 +++ 4 files changed, 210 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106038-3.c diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 3294c1e6274..5f7e40bd7a1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -75,6 +75,11 @@ (define_mode_iterator V_16_32_64 (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT") (V4HF "TARGET_64BIT") (V2SI "TARGET_64BIT") (V2SF "TARGET_64BIT")]) +(define_mode_iterator VI_16_32_64 + [V2QI V4QI V2HI + (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT") + (V2SI "TARGET_64BIT")]) + ;; V2S* modes (define_mode_iterator V2FI [V2SF V2SI]) @@ -86,6 +91,14 @@ (define_mode_attr mmxvecsize [(V8QI "b") (V4QI "b") (V2QI "b") (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")]) +;; Mapping to same size integral mode. +(define_mode_attr mmxinsnmode + [(V8QI "DI") (V4QI "SI") (V2QI "HI") + (V4HI "DI") (V2HI "SI") + (V2SI "DI") + (V4HF "DI") (V2HF "SI") + (V2SF "DI")]) + (define_mode_attr mmxdoublemode [(V8QI "V8HI") (V4HI "V4SI")]) @@ -350,22 +363,7 @@ (define_insn_and_split "*mov_imm" HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[1], mode); operands[1] = GEN_INT (val); - machine_mode mode; - switch (GET_MODE_SIZE (mode)) - { - case 2: - mode = HImode; - break; - case 4: - mode = SImode; - break; - case 8: - mode = DImode; - break; - default: - gcc_unreachable (); - } - operands[0] = lowpart_subreg (mode, operands[0], mode); + operands[0] = lowpart_subreg (mode, operands[0], mode); }) ;; For TARGET_64BIT we always round up to 8 bytes. @@ -2878,6 +2876,31 @@ (define_insn "mmx_andnot3" (set_attr "type" "mmxadd,sselog,sselog,sselog") (set_attr "mode" "DI,TI,TI,TI")]) +(define_insn "mmx_andnot3_gpr" + [(set (match_operand:MMXMODEI 0 "register_operand" "=?r,y,x,x,v") + (and:MMXMODEI + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "r,0,0,x,v")) + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "r,ym,x,x,v"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && (TARGET_MMX || TARGET_SSE2)" + "#" + [(set_attr "isa" "bmi,*,sse2_noavx,avx,avx512vl") + (set_attr "mmx_isa" "*,native,*,*,*") + (set_attr "type" "alu,mmxadd,sselog,sselog,sselog") + (set_attr "mode" "DI,DI,TI,TI,TI")]) + +(define_split + [(set (match_operand:MMXMODEI 0 "register_operand") + (and:MMXMODEI + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_mmxmem_operand")) + (match_operand:MMXMODEI 2 "register_mmxmem_operand"))) + (clobber (reg:CC FLAGS_REG))] + "reload_completed + && (TARGET_MMX || TARGET_MMX_WITH_SSE) + && !GENERAL_REGNO_P (REGNO (operands[0]))" + [(set (match_dup 0) + (and: (not: (match_dup 1)) (match_dup 2)))]) + (define_insn "*andnot3" [(set (match_operand:VI_16_32 0 "register_operand" "=?&r,?r,x,x,v") (and:VI_16_32 @@ -2892,20 +2915,20 @@ (define_insn "*andnot3" (set_attr "mode" "SI,SI,TI,TI,TI")]) (define_split - [(set (match_operand:VI_16_32 0 "general_reg_operand") - (and:VI_16_32 - (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand")) - (match_operand:VI_16_32 2 "general_reg_operand"))) + [(set (match_operand:VI_16_32_64 0 "general_reg_operand") + (and:VI_16_32_64 + (not:VI_16_32_64 (match_operand:VI_16_32_64 1 "general_reg_operand")) + (match_operand:VI_16_32_64 2 "general_reg_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI && reload_completed" [(parallel [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (and: (not: (match_dup 1)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] { - operands[2] = lowpart_subreg (SImode, operands[2], mode); - operands[1] = lowpart_subreg (SImode, operands[1], mode); - operands[0] = lowpart_subreg (SImode, operands[0], mode); + operands[2] = lowpart_subreg (mode, operands[2], mode); + operands[1] = lowpart_subreg (mode, operands[1], mode); + operands[0] = lowpart_subreg (mode, operands[0], mode); }) (define_split @@ -2948,14 +2971,28 @@ (define_expand "mmx_3" (match_operand:MMXMODEI 1 "register_mmxmem_operand") (match_operand:MMXMODEI 2 "register_mmxmem_operand")))] "TARGET_MMX || TARGET_MMX_WITH_SSE" - "ix86_fixup_binary_operands_no_copy (, mode, operands);") +{ + ix86_fixup_binary_operands_no_copy (, mode, operands); + if (TARGET_64BIT) + { + ix86_expand_binary_operator (, mode, operands); + DONE; + } +}) (define_expand "3" [(set (match_operand:MMXMODEI 0 "register_operand") (any_logic:MMXMODEI (match_operand:MMXMODEI 1 "register_operand") (match_operand:MMXMODEI 2 "register_operand")))] - "TARGET_MMX_WITH_SSE") + "TARGET_MMX_WITH_SSE" +{ + if (TARGET_64BIT) + { + ix86_expand_binary_operator (, mode, operands); + DONE; + } +}) (define_insn "*mmx_3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v") @@ -2974,6 +3011,32 @@ (define_insn "*mmx_3" (set_attr "type" "mmxadd,sselog,sselog,sselog") (set_attr "mode" "DI,TI,TI,TI")]) +(define_insn "*mmx_3_gpr" + [(set (match_operand:MMXMODEI 0 "register_operand" "=?r,y,x,x,v") + (any_logic:MMXMODEI + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,0,x,v") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "r,ym,x,x,v"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT && (TARGET_MMX || TARGET_SSE2) + && ix86_binary_operator_ok (, mode, operands)" + "#" + [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl") + (set_attr "mmx_isa" "*,native,*,*,*") + (set_attr "type" "alu,mmxadd,sselog,sselog,sselog") + (set_attr "mode" "DI,DI,TI,TI,TI")]) + +(define_split + [(set (match_operand:MMXMODEI 0 "register_operand") + (any_logic:MMXMODEI + (match_operand:MMXMODEI 1 "register_mmxmem_operand") + (match_operand:MMXMODEI 2 "register_mmxmem_operand"))) + (clobber (reg:CC FLAGS_REG))] + "reload_completed && (TARGET_MMX || TARGET_MMX_WITH_SSE) + && !GENERAL_REGNO_P (REGNO (operands[0]))" + [(set (match_dup 0) + (any_logic: (match_dup 1) + (match_dup 2)))]) + (define_insn "3" [(set (match_operand:VI_16_32 0 "register_operand" "=?r,x,x,v") (any_logic:VI_16_32 @@ -2987,20 +3050,20 @@ (define_insn "3" (set_attr "mode" "SI,TI,TI,TI")]) (define_split - [(set (match_operand:VI_16_32 0 "general_reg_operand") - (any_logic:VI_16_32 - (match_operand:VI_16_32 1 "general_reg_operand") - (match_operand:VI_16_32 2 "general_reg_operand"))) + [(set (match_operand:VI_16_32_64 0 "general_reg_operand") + (any_logic:VI_16_32_64 + (match_operand:VI_16_32_64 1 "general_reg_operand") + (match_operand:VI_16_32_64 2 "general_reg_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) - (any_logic:SI (match_dup 1) (match_dup 2))) + (any_logic: (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] { - operands[2] = lowpart_subreg (SImode, operands[2], mode); - operands[1] = lowpart_subreg (SImode, operands[1], mode); - operands[0] = lowpart_subreg (SImode, operands[0], mode); + operands[2] = lowpart_subreg (mode, operands[2], mode); + operands[1] = lowpart_subreg (mode, operands[1], mode); + operands[0] = lowpart_subreg (mode, operands[0], mode); }) (define_split diff --git a/gcc/testsuite/gcc.target/i386/pr106038-1.c b/gcc/testsuite/gcc.target/i386/pr106038-1.c new file mode 100644 index 00000000000..c026329c843 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106038-1.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-final { scan-assembler-not "xmm" { xfail *-*-* } } } */ + +void +foo (char* a, char* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; + a[2] &= b[2]; + a[3] &= b[3]; +} + +void +foo1 (char* a, char* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; +} + +void +foo2 (char* a, char* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; + a[2] &= b[2]; + a[3] &= b[3]; + a[4] &= b[4]; + a[5] &= b[5]; + a[6] &= b[6]; + a[7] &= b[7]; +} + +void +foo3 (char* a, char* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; + a[2] &= 3; + a[3] &= 3; +} + +void +foo4 (char* a, char* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; +} + +void +foo5 (char* a, char* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; + a[2] &= 2; + a[3] &= 3; + a[4] &= 4; + a[5] &= 5; + a[6] &= 6; + a[7] &= 7; +} diff --git a/gcc/testsuite/gcc.target/i386/pr106038-2.c b/gcc/testsuite/gcc.target/i386/pr106038-2.c new file mode 100644 index 00000000000..87d2070784f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106038-2.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2" } */ +/* { dg-final { scan-assembler-not "xmm" { xfail *-*-* } } } */ + +void +foo (short* a, short* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; + a[2] &= b[2]; + a[3] &= b[3]; +} + +void +foo1 (short* a, short* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; +} + +void +foo3 (short* a, short* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; + a[2] &= 3; + a[3] &= 3; +} + +void +foo4 (short* a, short* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; +} diff --git a/gcc/testsuite/gcc.target/i386/pr106038-3.c b/gcc/testsuite/gcc.target/i386/pr106038-3.c new file mode 100644 index 00000000000..91f7112395f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106038-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-msse2 -O2 -mtune=generic" } */ +/* { dg-final { scan-assembler-not "xmm" { xfail { ! ia32 } } } } */ + +void +foo1 (int* a, int* __restrict b) +{ + a[0] &= b[0]; + a[1] &= b[1]; +} + +void +foo4 (int* a, int* __restrict b) +{ + a[0] &= 1; + a[1] &= 2; +}