RISC-V: Make arch-24.c to test "success" case
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Commit Message
From: Tsukasa OI <research_trasio@irq.a4lg.com>
arch-24.c and arch-25.c are exactly the same and redundant. The author
suspects that the original author intended to test two base ISAs (RV32I and
RV64I) so this commit changes arch-24.c to test that RV32I+Zcf does not
cause any errors.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-24.c: Test RV32I+Zcf instead.
---
gcc/testsuite/gcc.target/riscv/arch-24.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
base-commit: 818cc9f2d2f3dbbd4004ff85d3125d92d1e430c9
Comments
On 8/28/23 21:31, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> arch-24.c and arch-25.c are exactly the same and redundant. The author
> suspects that the original author intended to test two base ISAs (RV32I and
> RV64I) so this commit changes arch-24.c to test that RV32I+Zcf does not
> cause any errors.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-24.c: Test RV32I+Zcf instead.
OK
jeff
@@ -1,5 +1,3 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+/* { dg-options "-march=rv32i_zcf -mabi=ilp32" } */
int foo() {}
-/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
-/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */