From patchwork Wed Jun 14 07:16:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Dapp X-Patchwork-Id: 107751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1053783vqr; Wed, 14 Jun 2023 00:17:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5bh6TP+yI05DnnvqSwpqYKnPf5VyFTRoZyMXCi3RHewvwh2IQwhcvfNKdIapSl3TKI8wOr X-Received: by 2002:a17:906:7951:b0:94e:e97b:c65 with SMTP id l17-20020a170906795100b0094ee97b0c65mr16601524ejo.60.1686727025732; Wed, 14 Jun 2023 00:17:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686727025; cv=none; d=google.com; s=arc-20160816; b=lpCRAZj0ZZvSnKK/jNKIZrIeTLOVrvFcI7Rns1ybqTeeeYgK2pd1cxKtiWnAl4dhTs 5m/TVvmhw8OVV8jMUCh1AXZtxcLOLXTfg23SakJAuCcnQi6kjuaUf8F328AwSMPFuQZk D+Hy3PUGYgwsIjjK8o5ttu9bxyMVC9Jt9mcftZIKqHKQqbf2OwtYFAuoxzonoOCGnIrU YUDMF5tAVxuiAKMtT/khxvD3/l7TT5gDzatGK2yQ4vbRiBEPXQaVUFUDM0C5k/jb3E2l +8Eox3AOG+uljM+ur9dVURLjRkgxLE3VFcj8KbafDsHHWEU6tiLYnOcTf/OUUd28vJC7 TLRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:subject:to:content-language:cc:user-agent :mime-version:date:message-id:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=/SHqhxkUbQYVpYbIpaeRPafh7os2wUIh/u57hlP5APQ=; b=j/TyJK0va57M8FZm/YPA6kQIwtCDgJHu+g2S15n+OS8zOzzpHc/4tzXq6VDH6popzG iZ6Sn/cA+eodVKr6TG4BCt/nqDwcyxqsZ6WEycJTsX1E73Dd1tXEYM0N00YRAXeAawhW 7d7+ugfPxaxV+u3OPzpZaArVWhAP7JBFYQkpIHLoubRuxXOkPYuUbho1PgWr5aVSlF/T lnSt6C3UsG4y31pyaKdNwTJP8dmYtRqdsFagHq3ItOlzfrPCJDHnAfCzLlZB8RuoiL9E u8sDOlCIp+DRxZj8H05+FiDlzGPRmozAwAHV/jjrmAbyytf6NMh0ZdSQOl0l6J67uW4/ JsjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=AIOKKQbI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l9-20020a170906644900b00965a6d6b536si7757615ejn.335.2023.06.14.00.17.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 00:17:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=AIOKKQbI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 44EE2385842A for ; Wed, 14 Jun 2023 07:17:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 44EE2385842A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686727024; bh=/SHqhxkUbQYVpYbIpaeRPafh7os2wUIh/u57hlP5APQ=; h=Date:Cc:To:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=AIOKKQbIumusjzWi63om4mD/0EEh2PbD1FSV7TY1vcIL1jrW8pFm7oCDdAClfu3YW It5yr+ZFg+JnpWp1OTPO5wdTDJjJPhWvU/ZNjUKGF519PIzRK42FPAXqEr+YostIh7 B23CwdVMRdLvBUQTk1A7qfZFNeaShDrk0wrNRu74= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 325613858D38 for ; Wed, 14 Jun 2023 07:16:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 325613858D38 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-98276e2a4bbso27106066b.0 for ; Wed, 14 Jun 2023 00:16:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686726975; x=1689318975; h=content-transfer-encoding:subject:from:to:content-language:cc :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/SHqhxkUbQYVpYbIpaeRPafh7os2wUIh/u57hlP5APQ=; b=Ierns8PU026O1eufAM9k3k6E4sAcGrgh9mUrnUW1cNTjoy7Li81FZBIc5dTA6+Ix64 XEt+q8HqtA5cWIV4EIJPLKs/lZacj7HKqNK7LhWMGhNcxQFkxz++pqf7mr/GjIGqqc6M szR3pTMCPd6VsddU55oeKVI5Xv9a9IKbgC46oNn3dUw3F/hCEr10pT9VfGPUfMzjibtY mTNuEz3yNmrrFxhq/iq0D7MWfDwMelcRPEYZR1EpLTNWBcd7hQ1/YIsRn6RxSKCZwFcf XjJWqNJnRZwanrpTjfnEvNNRhlhvgb0auFxXhN66+m9TU9vMxCCf60qoNM4UVuXyxa7k GSGw== X-Gm-Message-State: AC+VfDwnVzaeGlWKcS8gxy+WgxSU4zyIvJEWv+DfseGy9zCkmB2Ti5z3 dveni9ocEHJOxtVACAEQoROWi+I/uH8= X-Received: by 2002:a17:907:6d04:b0:974:326b:f9b2 with SMTP id sa4-20020a1709076d0400b00974326bf9b2mr14741378ejc.66.1686726974991; Wed, 14 Jun 2023 00:16:14 -0700 (PDT) Received: from [192.168.1.23] (ip-046-005-130-086.um12.pools.vodafone-ip.de. [46.5.130.86]) by smtp.gmail.com with ESMTPSA id fi5-20020a170906da0500b00965d294e633sm7642164ejb.58.2023.06.14.00.16.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jun 2023 00:16:14 -0700 (PDT) Message-ID: <1b161ee0-1b7c-3c39-1015-ba5859f57a7a@gmail.com> Date: Wed, 14 Jun 2023 09:16:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Cc: rdapp.gcc@gmail.com Content-Language: en-US To: gcc-patches , palmer , Kito Cheng , "juzhe.zhong@rivai.ai" , jeffreyalaw Subject: [PATCH] RISC-V: Add (u)int8_t to binop tests. X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768661477851587562?= X-GMAIL-MSGID: =?utf-8?q?1768661477851587562?= Hi, this patch adds the missing (u)int8_t types to the binop tests. I suggest in the future we have the testsuite pass -march=rv32gcv as well as -march=rv64gcv as options to each test case instead of essentially duplicate the files as we do now. Regards Robin gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for (u)int8_t. * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito. * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito. * gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito. --- .../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c | 10 +++------- .../gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c | 6 +++--- .../riscv/rvv/autovec/binop/shift-template.h | 5 ++++- .../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 6 ++++++ .../gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vadd-template.h | 7 ++++++- .../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 6 ++++++ .../gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vand-template.h | 7 ++++++- .../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/binop/vdiv-template.h | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vmax-template.h | 3 ++- .../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vmin-template.h | 3 ++- .../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-template.h | 3 ++- .../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 6 ++++++ .../gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vor-template.h | 7 ++++++- .../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 4 ++++ .../gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c | 6 +++--- .../gcc.target/riscv/rvv/autovec/binop/vrem-template.h | 5 ++++- .../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 8 ++++++++ .../gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vsub-template.h | 5 ++++- .../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 6 ++++++ .../gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c | 4 ++-- .../gcc.target/riscv/rvv/autovec/binop/vxor-template.h | 7 ++++++- 44 files changed, 150 insertions(+), 62 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c index ff3633b530a..d7052b2270c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c @@ -32,12 +32,16 @@ assert (as##TYPE[i] == (VAL >> (i % 4))); #define RUN_ALL() \ + RUN(int8_t, 1) \ + RUN(uint8_t, 2) \ RUN(int16_t, 1) \ RUN(uint16_t, 2) \ RUN(int32_t, 3) \ RUN(uint32_t, 4) \ RUN(int64_t, 5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c index 557a7c82531..befa4b85e8f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c @@ -3,10 +3,6 @@ #include "shift-template.h" -/* TODO: For int16_t and uint16_t we need widening/promotion patterns. - We don't check the assembler number since lacking patterns make - auto-vectorization inconsistent in LMUL = 1/2/4/8. */ - -/* { dg-final { scan-assembler {\tvsll\.vv} } } */ -/* { dg-final { scan-assembler {\tvsrl\.vv} } } */ -/* { dg-final { scan-assembler {\tvsra\.vv} } } */ +/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c index 01a9cb21efc..976b29fa356 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c @@ -3,6 +3,6 @@ #include "shift-template.h" -/* { dg-final { scan-assembler-times {\tvsll\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h index 16ae48c8ede..ca1b96f9f25 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h @@ -16,14 +16,17 @@ dst[i] = a[i] >> b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST1_TYPE(int8_t) \ + TEST1_TYPE(uint8_t) \ TEST1_TYPE(int16_t) \ TEST1_TYPE(uint16_t) \ TEST1_TYPE(int32_t) \ TEST1_TYPE(uint32_t) \ TEST1_TYPE(int64_t) \ TEST1_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c index 8bdc7a220c3..4f6c8e773c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c @@ -44,18 +44,24 @@ assert (aim##TYPE[i] == VAL - 16); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, -11) \ RUN2(uint64_t, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ RUN3M(int16_t, 13) \ RUN3(uint16_t, 14) \ RUN3M(int32_t, 15) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c index 799ed27ec6d..2d094749c6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c @@ -3,5 +3,5 @@ #include "vadd-template.h" -/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c index 64c2eeec7cf..4a1dc41c34a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c @@ -3,5 +3,5 @@ #include "vadd-template.h" -/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h index cd945d471d2..fecf2947691 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h @@ -32,20 +32,25 @@ dst[i] = a[i] - 16; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ TEST3M_TYPE(int16_t) \ TEST3_TYPE(uint16_t) \ TEST3M_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c index c13755ed06a..3fa6cf35e18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c @@ -44,18 +44,24 @@ assert (aim##TYPE[i] == (VAL & -16)); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, -11) \ RUN2(uint64_t, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ RUN3M(int16_t, 13) \ RUN3(uint16_t, 14) \ RUN3M(int32_t, 15) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c index 24fc70b4ea4..f7636abdec0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c @@ -3,5 +3,5 @@ #include "vand-template.h" -/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c index 67f37c1e170..dee8a2d6124 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c @@ -3,5 +3,5 @@ #include "vand-template.h" -/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h index 5cabe073097..e2409594f39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h @@ -32,20 +32,25 @@ dst[i] = a[i] & -16; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ TEST3M_TYPE(int16_t) \ TEST3_TYPE(uint16_t) \ TEST3M_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c index 5de339172fc..c4fd81f4bf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c @@ -28,12 +28,16 @@ assert (as##TYPE[i] == 5); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 1dce9dd562e..9f059ebc84c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -4,7 +4,7 @@ #include "vdiv-template.h" /* Currently we use an epilogue loop which also contains vdivs. Therefore we - expect 10 vdiv[u]s instead of 6. */ + expect 14 vdiv[u]s instead of 8. */ -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index 16a18c466e0..cd5d30b8974 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -4,7 +4,7 @@ #include "vdiv-template.h" /* Currently we use an epilogue loop which also contains vdivs. Therefore we - expect 10 vdiv[u]s instead of 6. */ + expect 14 vdiv[u]s instead of 8. */ -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h index f8d3bfde4ed..fd9199722b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h @@ -17,12 +17,16 @@ } #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c index cf184e24b1e..668f848694b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c @@ -28,12 +28,16 @@ assert (as##TYPE[i] == 0 > VAL ? 0 : VAL); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c index 46a321289fc..c10b77672d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c @@ -3,5 +3,5 @@ #include "vmax-template.h" -/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 7 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c index 9bbaf763157..2f7d9faa046 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c @@ -3,5 +3,5 @@ #include "vmax-template.h" -/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 7 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h index fc6a07e3ce9..afefa30ca68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h @@ -16,8 +16,9 @@ dst[i] = a[i] > b ? a[i] : b; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c index b461f8ba484..63c05a119a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c @@ -28,12 +28,16 @@ assert (as##TYPE[i] == 0 < VAL ? 0 : VAL); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c index da3bb179ba7..5d8a7277713 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c @@ -3,5 +3,5 @@ #include "vmin-template.h" -/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 7 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c index 07278b22b2d..1d3760b614f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c @@ -3,5 +3,5 @@ #include "vmin-template.h" -/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 7 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 7 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h index 06f6b95461e..70007a9195f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h @@ -16,8 +16,9 @@ dst[i] = a[i] < b ? a[i] : b; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c index e8441c0605b..ca0dc9130e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c @@ -28,12 +28,16 @@ assert (as##TYPE[i] == 3 * VAL); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c index f4df04d15eb..55a0bf9188d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c @@ -3,4 +3,4 @@ #include "vmul-template.h" -/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c index f436b8a82a8..9f8b424c4c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c @@ -3,4 +3,4 @@ #include "vmul-template.h" -/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h index 37f77972101..d428341804e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h @@ -16,8 +16,9 @@ dst[i] = a[i] * b; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c index 5401e8d3ecd..f6b3770dcbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c @@ -44,18 +44,24 @@ assert (aim##TYPE[i] == (VAL | -16)); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, -11) \ RUN2(uint64_t, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ RUN3M(int16_t, 13) \ RUN3(uint16_t, 14) \ RUN3M(int32_t, 15) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c index fc76d1c3b3e..70ea8ef65cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c @@ -3,5 +3,5 @@ #include "vor-template.h" -/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c index ae115a2f503..44d09a2bddc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c @@ -3,5 +3,5 @@ #include "vor-template.h" -/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h index e60146cc232..3daad2e8890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h @@ -32,20 +32,25 @@ dst[i] = a[i] | -16; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ TEST3M_TYPE(int16_t) \ TEST3_TYPE(uint16_t) \ TEST3M_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c index 4a4c064e101..58b69ec393e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c @@ -28,12 +28,16 @@ assert (as##TYPE[i] == 89 % VAL); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c index df99f5019fb..7d2b478e1de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c @@ -4,7 +4,7 @@ #include "vrem-template.h" /* Currently we use an epilogue loop which also contains vrems. Therefore we - expect 10 vrem[u]s instead of 6. */ + expect 14 vrem[u]s instead of 8. */ -/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c index 3cff13a47e4..b7bc1ccb860 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c @@ -4,7 +4,7 @@ #include "vrem-template.h" /* Currently we use an epilogue loop which also contains vrems. Therefore we - expect 10 vrem[u]s instead of 6. */ + expect 14 vrem[u]s instead of 8. */ -/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h index d5ef40667ff..9c4e6acae99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h @@ -16,14 +16,17 @@ dst[i] = a[i] % b; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index 4f254872e33..f024eb0c04b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -44,24 +44,32 @@ assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667))); #define RUN_ALL() \ + RUN(int8_t, 1) \ + RUN(uint8_t, 2) \ RUN(int16_t, 1) \ RUN(uint16_t, 2) \ RUN(int32_t, 3) \ RUN(uint32_t, 4) \ RUN(int64_t, 5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, 7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, 7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, 9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, 11) \ RUN2(uint64_t, 12) \ + RUN3(int8_t) \ + RUN3(uint8_t) \ RUN3(int16_t) \ RUN3(uint16_t) \ RUN3(int32_t) \ RUN3(uint32_t) \ RUN3(int64_t) \ RUN3(uint64_t) \ + RUN4(int8_t) \ + RUN4(uint8_t) \ RUN4(int16_t) \ RUN4(uint16_t) \ RUN4(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c index a0d3802be65..e8f23b100a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c @@ -3,5 +3,5 @@ #include "vsub-template.h" -/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c index 562c026a7e4..0e20a8c34b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c @@ -3,5 +3,5 @@ #include "vsub-template.h" -/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 14 } } */ +/* { dg-final { scan-assembler-times {\tvrsub\.vi} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h index 47f07f13462..a0e8d8964cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h @@ -32,8 +32,9 @@ dst[i] = 15 - a[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -46,6 +47,8 @@ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) + TEST3_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ TEST3_TYPE(int16_t) \ TEST3_TYPE(uint16_t) \ TEST3_TYPE(int32_t) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c index ab0975a6408..7239733d12c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c @@ -44,18 +44,24 @@ assert (aim##TYPE[i] == (VAL ^ -16)); #define RUN_ALL() \ + RUN(int8_t, -1) \ + RUN(uint8_t, 2) \ RUN(int16_t, -1) \ RUN(uint16_t, 2) \ RUN(int32_t, -3) \ RUN(uint32_t, 4) \ RUN(int64_t, -5) \ RUN(uint64_t, 6) \ + RUN2(int8_t, -7) \ + RUN2(uint8_t, 8) \ RUN2(int16_t, -7) \ RUN2(uint16_t, 8) \ RUN2(int32_t, -9) \ RUN2(uint32_t, 10) \ RUN2(int64_t, -11) \ RUN2(uint64_t, 12) \ + RUN3M(int8_t, 13) \ + RUN3(uint8_t, 14) \ RUN3M(int16_t, 13) \ RUN3(uint16_t, 14) \ RUN3M(int32_t, 15) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c index fbef4a45770..83b223e987f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c @@ -3,5 +3,5 @@ #include "vxor-template.h" -/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c index 9729ad14eb1..6ba007c9d90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c @@ -3,5 +3,5 @@ #include "vxor-template.h" -/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */ -/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h index 370b242f197..b36698b5311 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h @@ -32,20 +32,25 @@ dst[i] = a[i] ^ -16; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ TEST_TYPE(uint32_t) \ TEST_TYPE(int64_t) \ TEST_TYPE(uint64_t) \ + TEST2_TYPE(int8_t) \ + TEST2_TYPE(uint8_t) \ TEST2_TYPE(int16_t) \ TEST2_TYPE(uint16_t) \ TEST2_TYPE(int32_t) \ TEST2_TYPE(uint32_t) \ TEST2_TYPE(int64_t) \ TEST2_TYPE(uint64_t) \ + TEST3M_TYPE(int8_t) \ + TEST3_TYPE(uint8_t) \ TEST3M_TYPE(int16_t) \ TEST3_TYPE(uint16_t) \ TEST3M_TYPE(int32_t) \