diff mbox series

[3/3] Fix PR 106690: enable effective_target_bswap for RISCV targets with ZBB enabled by default

Message ID 1661015666-14659-4-git-send-email-apinski@marvell.com
State New, archived
Headers
Series Improve bswap for ZBB |

Commit Message

Li, Pan2 via Gcc-patches Aug. 20, 2022, 5:14 p.m. UTC 
  From: Andrew Pinski <apinski@marvell.com>

While looking for testcases to quickly test, I Noticed that
check_effective_target_bswap was not enabled for riscv when
ZBB is enabled. This patch checks if ZBB is enabled when
targeting RISCV* for bswap.

OK? Ran the testsuite for riscv32-linux-gnu both with and without ZBB enabled.

PR testsuite/106690
gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (check_effective_target_bswap):
	Return true if riscv and ZBB ISA extension is enabled.

Change-Id: I521c91e7fc1a54faa0c8399b685248690022278b
---
 gcc/testsuite/lib/target-supports.exp | 7 +++++++
 1 file changed, 7 insertions(+)
diff mbox series

Patch

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 04a2a8e8659..0f1e1af31e9 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8646,6 +8646,13 @@  proc check_effective_target_bswap { } {
 	     || [istarget powerpc*-*-*]
 	     || [istarget rs6000-*-*]
 	     || [istarget s390*-*-*]
+	     || ([istarget riscv*-*-*]
+	         && [check_no_compiler_messages_nocache riscv_zbb object {
+		     #if __riscv_zbb  <= 0
+		     #error ZBB is not enabled
+		     #endif
+		     int i;
+		 } ""])
 	     || ([istarget arm*-*-*]
 		 && [check_no_compiler_messages_nocache arm_v6_or_later object {
 		     #if __ARM_ARCH < 6