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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id g13-20020a056402090d00b004405af7da47si5612871edz.564.2022.08.20.10.15.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Aug 2022 10:15:48 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="R/DR5ixC"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 140C4385782C for ; Sat, 20 Aug 2022 17:15:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 140C4385782C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1661015721; bh=xSUlfKTa4w1Jionl1EkhNXbYuFZ5UVOLidnRSvEzgEQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=R/DR5ixC0Tk1sAwUfMZPxUuaryj7uDG82N6H6rMChBxdJCahc0Z7CkfWZWYKez+em QCs3uro6GH9MrOrEhVO+3UeQZLhXPGUQw1r0QaRzUQDE5upaNLuamXkMxreEiSXkQ6 Pho6+DfBk+nZcrNmhWC0tjeR3yZv7neQ151LKRGU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by sourceware.org (Postfix) with ESMTPS id CE5223858C83 for ; Sat, 20 Aug 2022 17:14:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CE5223858C83 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27KH0CPS017197 for ; Sat, 20 Aug 2022 10:14:34 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3j2y4jrm0k-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 20 Aug 2022 10:14:34 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 20 Aug 2022 10:14:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 20 Aug 2022 10:14:32 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 5C4ED5B6937; Sat, 20 Aug 2022 10:14:32 -0700 (PDT) To: Subject: [PATCH 2/3] Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled Date: Sat, 20 Aug 2022 10:14:25 -0700 Message-ID: <1661015666-14659-3-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1661015666-14659-1-git-send-email-apinski@marvell.com> References: <1661015666-14659-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: vW2JKUmW4rMu7OBp8W8719yHDaCYvnpU X-Proofpoint-ORIG-GUID: vW2JKUmW4rMu7OBp8W8719yHDaCYvnpU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-20_08,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-14.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741701249442947324?= X-GMAIL-MSGID: =?utf-8?q?1741701249442947324?= From: Andrew Pinski The default expansion for bswap16 is two extractions (shift/and) followed by an insertation (ior) and then a zero extend. This can be improved with ZBB enabled to just full byteswap followed by a (logical) shift right. This patch adds a new pattern for this which does that. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: PR target/106601 * config/riscv/bitmanip.md (bswaphi2): New pattern. gcc/testsuite/ChangeLog: PR target/106601 * gcc.target/riscv/zbb_32_bswap-2.c: New test. * gcc.target/riscv/zbb_bswap-2.c: New test. Change-Id: If61362c14664cf8685da17779217033689878f86 --- gcc/config/riscv/bitmanip.md | 24 +++++++++++++++++++ .../gcc.target/riscv/zbb_32_bswap-2.c | 12 ++++++++++ gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c | 12 ++++++++++ 3 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index c7ba667f87a..c4383285d81 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -276,6 +276,30 @@ (define_insn "bswap2" "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) +;; HI bswap can be emulated using SI/DI bswap followed +;; by a logical shift right +;; SI bswap for TARGET_64BIT is already similarly in +;; the common code. +(define_expand "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (bswap:HI (match_operand:HI 1 "register_operand" "r")))] + "TARGET_ZBB" +{ + rtx tmp = gen_reg_rtx (word_mode); + rtx newop1 = gen_lowpart (word_mode, operands[1]); + if (TARGET_64BIT) + emit_insn (gen_bswapdi2 (tmp, newop1)); + else + emit_insn (gen_bswapsi2 (tmp, newop1)); + rtx tmp1 = gen_reg_rtx (word_mode); + if (TARGET_64BIT) + emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16))); + else + emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16))); + emit_move_insn (operands[0], gen_lowpart (HImode, tmp1)); + DONE; +}) + (define_insn "3" [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_minmax:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c new file mode 100644 index 00000000000..679b34c4e41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_32_bswap-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap16(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler "srli" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c new file mode 100644 index 00000000000..c358f6683f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +int foo(int n) +{ + return __builtin_bswap16(n); +} + +/* { dg-final { scan-assembler "rev8" } } */ +/* { dg-final { scan-assembler "srli" } } */ +