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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cs14-20020a0564020c4e00b004407104243csi1801751edb.153.2022.08.18.15.10.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Aug 2022 15:10:00 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=dn0GkCiR; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9FBDD3857B82 for ; Thu, 18 Aug 2022 22:09:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9FBDD3857B82 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860540; bh=AlD7vlW7UeQUOxJGdUzLgSn1CqFE/eVk2C2sj4hHIUk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=dn0GkCiRbWY0Bx8LAfFikXwKQxb80vNrNrpfpzuCOncgin4EqjbBHQ631T6GG1QpK kRHVig/AEA3HyF6Nu6yAYunlTNm722m4wwxC7wji55gvfu97oNRJYVXgdyUs5pmL3A X8UbdLvPcf/gRE5UxOcgYjcP5KDkdrbA0WWpgX9o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 3C5E0385829E for ; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3C5E0385829E Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHpqwL001624 for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wn-8 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Aug 2022 15:04:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:02 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 896793F7070; Thu, 18 Aug 2022 15:04:02 -0700 (PDT) To: Subject: [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it Date: Thu, 18 Aug 2022 15:03:48 -0700 Message-ID: <1660860233-11175-6-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Ypbohd731cWvGwfKub-WaEOwzg8BZG04 X-Proofpoint-GUID: Ypbohd731cWvGwfKub-WaEOwzg8BZG04 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: apinski--- via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: apinski@marvell.com Cc: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1741538565652272060?= X-GMAIL-MSGID: =?utf-8?q?1741538565652272060?= From: Andrew Pinski To make things easier and more maintainable, we need to add support printing out w if TARGET_64BIT so this patch adds %~ to do that, similar how the x86 backend uses %~ to print out i/f for TARGET_AVX2. We could have chosen any punctuation symbol but ~ looks the closest to w. OK? Build and tested for riscv64-linux-gnu and riscv32-linux-gnu with no regressions. Thanks, Andrew Pinski gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Handle '~'. (riscv_print_operand_punct_valid_p): New function (TARGET_PRINT_OPERAND_PUNCT_VALID_P): Define. * config/riscv/bitmanip.md (si2/clz_ctz_pcnt): Use %~ instead of conditional the pattern on TARGET_64BIT. (rotrsi3): Likewise. (rotlsi3): Likewise. * config/riscv/riscv.md: Add ~ to the list of modifiers. (addsi3): Use %~ instead of conditional the pattern on TARGET_64BIT. (subsi3): Likewise. (negsi2): Likewise. (mulsi3): Likewise. (optab>si3/any_div): Likewise. (*addhi3): Likewise. (si3/any_shift): Likewise. --- gcc/config/riscv/bitmanip.md | 6 +++--- gcc/config/riscv/riscv.cc | 19 +++++++++++++++++++ gcc/config/riscv/riscv.md | 15 ++++++++------- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 3329dd54eb6..ebd6eee1a22 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -143,7 +143,7 @@ (define_insn "si2" [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "w\t%0,%1" : "\t%0,%1"; } + "%~\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) @@ -201,7 +201,7 @@ (define_insn "rotrsi3" (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] "TARGET_ZBB" - { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; } + "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotrdi3" @@ -225,7 +225,7 @@ (define_insn "rotlsi3" (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] "TARGET_ZBB" - { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; } + "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) (define_insn "rotldi3" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 189be5e4e6f..22d0f6d604c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3731,12 +3731,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. 'T' Print shift-index of inverted single-bit mask OP. + '~' Print w if TARGET_64BIT is true; otherwise not print anything. Note please keep this list and the list in riscv.md in sync. */ static void riscv_print_operand (FILE *file, rtx op, int letter) { + /* `~` does not take an operand so op will be null + Check for before accessing op. + */ + if (letter == '~') + { + if (TARGET_64BIT) + fputc('w', file); + return; + } machine_mode mode = GET_MODE (op); enum rtx_code code = GET_CODE (op); @@ -3812,6 +3822,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) } } +/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */ +static bool +riscv_print_operand_punct_valid_p (unsigned char code) +{ + return (code == '~'); +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ static void @@ -5900,6 +5917,8 @@ riscv_init_libfuncs (void) #define TARGET_PRINT_OPERAND riscv_print_operand #undef TARGET_PRINT_OPERAND_ADDRESS #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address +#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P +#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p #undef TARGET_SETUP_INCOMING_VARARGS #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index aad2836d179..30cd07dc6f5 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -32,6 +32,7 @@ ;; i -- Print i if the operand is not a register. ;; S -- Print shift-index of single-bit mask OP. ;; T -- Print shift-index of inverted single-bit mask OP. +;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything. (define_c_enum "unspec" [ ;; Override return address for exception handling. @@ -312,7 +313,7 @@ (define_insn "addsi3" (plus:SI (match_operand:SI 1 "register_operand" " r,r") (match_operand:SI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -452,7 +453,7 @@ (define_insn "subsi3" (minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ") (match_operand:SI 2 "register_operand" " r")))] "" - { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; } + "sub%~\t%0,%z1,%2" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -568,7 +569,7 @@ (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "register_operand" " r")))] "" - { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; } + "neg%~\t%0,%1" [(set_attr "type" "arith") (set_attr "mode" "SI")]) @@ -613,7 +614,7 @@ (define_insn "mulsi3" (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_MUL" - { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } + "mul%~\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -883,7 +884,7 @@ (define_insn "si3" (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] "TARGET_DIV" - { return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; } + "%i2%~\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -1605,7 +1606,7 @@ (define_insn "*addhi3" (plus:HI (match_operand:HISI 1 "register_operand" " r,r") (match_operand:HISI 2 "arith_operand" " r,I")))] "" - { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; } + "add%i2%~\t%0,%1,%2" [(set_attr "type" "arith") (set_attr "mode" "HI")]) @@ -1787,7 +1788,7 @@ (define_insn "si3" operands[2] = GEN_INT (INTVAL (operands[2]) & (GET_MODE_BITSIZE (SImode) - 1)); - return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; + return "%i2%~\t%0,%1,%2"; } [(set_attr "type" "shift") (set_attr "mode" "SI")])