@@ -143,7 +143,7 @@ (define_insn "<bitmanip_optab>si2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
+ "<bitmanip_insn>%~\t%0,%1"
[(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
@@ -201,7 +201,7 @@ (define_insn "rotrsi3"
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "arith_operand" "rI")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
+ "ror%i2%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
(define_insn "rotrdi3"
@@ -225,7 +225,7 @@ (define_insn "rotlsi3"
(rotate:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")))]
"TARGET_ZBB"
- { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
+ "rol%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
(define_insn "rotldi3"
@@ -3731,12 +3731,22 @@ riscv_memmodel_needs_release_fence (enum memmodel model)
'i' Print i if the operand is not a register.
'S' Print shift-index of single-bit mask OP.
'T' Print shift-index of inverted single-bit mask OP.
+ '~' Print w if TARGET_64BIT is true; otherwise not print anything.
Note please keep this list and the list in riscv.md in sync. */
static void
riscv_print_operand (FILE *file, rtx op, int letter)
{
+ /* `~` does not take an operand so op will be null
+ Check for before accessing op.
+ */
+ if (letter == '~')
+ {
+ if (TARGET_64BIT)
+ fputc('w', file);
+ return;
+ }
machine_mode mode = GET_MODE (op);
enum rtx_code code = GET_CODE (op);
@@ -3812,6 +3822,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
}
}
+/* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */
+static bool
+riscv_print_operand_punct_valid_p (unsigned char code)
+{
+ return (code == '~');
+}
+
/* Implement TARGET_PRINT_OPERAND_ADDRESS. */
static void
@@ -5900,6 +5917,8 @@ riscv_init_libfuncs (void)
#define TARGET_PRINT_OPERAND riscv_print_operand
#undef TARGET_PRINT_OPERAND_ADDRESS
#define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
+#undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
+#define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
@@ -32,6 +32,7 @@
;; i -- Print i if the operand is not a register.
;; S -- Print shift-index of single-bit mask OP.
;; T -- Print shift-index of inverted single-bit mask OP.
+;; ~ -- Print w if TARGET_64BIT is true; otherwise not print anything.
(define_c_enum "unspec" [
;; Override return address for exception handling.
@@ -312,7 +313,7 @@ (define_insn "addsi3"
(plus:SI (match_operand:SI 1 "register_operand" " r,r")
(match_operand:SI 2 "arith_operand" " r,I")))]
""
- { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
+ "add%i2%~\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -452,7 +453,7 @@ (define_insn "subsi3"
(minus:SI (match_operand:SI 1 "reg_or_0_operand" " rJ")
(match_operand:SI 2 "register_operand" " r")))]
""
- { return TARGET_64BIT ? "subw\t%0,%z1,%2" : "sub\t%0,%z1,%2"; }
+ "sub%~\t%0,%z1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -568,7 +569,7 @@ (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" " r")))]
""
- { return TARGET_64BIT ? "negw\t%0,%1" : "neg\t%0,%1"; }
+ "neg%~\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
@@ -613,7 +614,7 @@ (define_insn "mulsi3"
(mult:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_MUL"
- { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
+ "mul%~\t%0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -883,7 +884,7 @@ (define_insn "<optab>si3"
(any_div:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
"TARGET_DIV"
- { return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2"; }
+ "<insn>%i2%~\t%0,%1,%2"
[(set_attr "type" "idiv")
(set_attr "mode" "SI")])
@@ -1605,7 +1606,7 @@ (define_insn "*add<mode>hi3"
(plus:HI (match_operand:HISI 1 "register_operand" " r,r")
(match_operand:HISI 2 "arith_operand" " r,I")))]
""
- { return TARGET_64BIT ? "add%i2w\t%0,%1,%2" : "add%i2\t%0,%1,%2"; }
+ "add%i2%~\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "HI")])
@@ -1787,7 +1788,7 @@ (define_insn "<optab>si3"
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (SImode) - 1));
- return TARGET_64BIT ? "<insn>%i2w\t%0,%1,%2" : "<insn>%i2\t%0,%1,%2";
+ return "<insn>%i2%~\t%0,%1,%2";
}
[(set_attr "type" "shift")
(set_attr "mode" "SI")])