diff mbox series

rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]

Message ID 124c676e-27ed-252e-3f33-0f9b370ef08e@linux.ibm.com
State Accepted
Headers
Series rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932] |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Kewen.Lin June 6, 2023, 9:19 a.m. UTC 
  Hi,

As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
should be guarded under vsx rather than power7, as their
corresponding bif patterns have the conditions TARGET_VSX
and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
their supports.

Bootstrapped and regtested on powerpc64-linux-gnu P7/P8/P9 and
powerpc64le-linux-gnu P9 and P10.

I'll push this next week if no objections.

BR,
Kewen
-----
	PR target/109932

gcc/ChangeLog:

	* config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
	__builtin_unpack_vector_int128): Move from stanza power7 to vsx.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr109932-1.c: New test.
	* gcc.target/powerpc/pr109932-2.c: New test.
---
 gcc/config/rs6000/rs6000-builtins.def         | 14 +++++++-------
 gcc/testsuite/gcc.target/powerpc/pr109932-1.c | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/pr109932-2.c | 16 ++++++++++++++++
 3 files changed, 39 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-1.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-2.c

--
2.25.1

Comments

David Edelsohn June 11, 2023, 6:39 p.m. UTC | #1 
On Tue, Jun 6, 2023 at 5:19 AM Kewen.Lin <linkw@linux.ibm.com> wrote:

> Hi,
>
> As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
> should be guarded under vsx rather than power7, as their
> corresponding bif patterns have the conditions TARGET_VSX
> and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
> move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
> their supports.
>
> Bootstrapped and regtested on powerpc64-linux-gnu P7/P8/P9 and
> powerpc64le-linux-gnu P9 and P10.
>
> I'll push this next week if no objections.
>
> BR,
> Kewen
> -----
>         PR target/109932
>
> gcc/ChangeLog:
>
>         * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
>         __builtin_unpack_vector_int128): Move from stanza power7 to vsx.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/powerpc/pr109932-1.c: New test.
>         * gcc.target/powerpc/pr109932-2.c: New test.
>

This is okay.

Thanks, David


> ---
>  gcc/config/rs6000/rs6000-builtins.def         | 14 +++++++-------
>  gcc/testsuite/gcc.target/powerpc/pr109932-1.c | 16 ++++++++++++++++
>  gcc/testsuite/gcc.target/powerpc/pr109932-2.c | 16 ++++++++++++++++
>  3 files changed, 39 insertions(+), 7 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-1.c
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-2.c
>
> diff --git a/gcc/config/rs6000/rs6000-builtins.def
> b/gcc/config/rs6000/rs6000-builtins.def
> index 92d9b46e1b9..a38184b0ef9 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2009,6 +2009,13 @@
>    const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
>      XXSPLTD_V2DI vsx_xxspltd_v2di {}
>
> +  const vsq __builtin_pack_vector_int128 (unsigned long long, \
> +                                          unsigned long long);
> +    PACK_V1TI packv1ti {}
> +
> +  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
> +    UNPACK_V1TI unpackv1ti {}
> +
>
>  ; Power7 builtins (ISA 2.06).
>  [power7]
> @@ -2030,16 +2037,9 @@
>    const unsigned int __builtin_divweu (unsigned int, unsigned int);
>      DIVWEU diveu_si {}
>
> -  const vsq __builtin_pack_vector_int128 (unsigned long long, \
> -                                          unsigned long long);
> -    PACK_V1TI packv1ti {}
> -
>    void __builtin_ppc_speculation_barrier ();
>      SPECBARR speculation_barrier {}
>
> -  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
> -    UNPACK_V1TI unpackv1ti {}
> -
>
>  ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
>  [power7-64]
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
> b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
> new file mode 100644
> index 00000000000..3e3f9eaa65e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-maltivec -mno-vsx" } */
> +
> +/* Verify there is no ICE but one expected error message instead.  */
> +
> +#include <altivec.h>
> +
> +extern vector signed __int128 res_vslll;
> +extern unsigned long long aull[2];
> +
> +void
> +testVectorInt128Pack ()
> +{
> +  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* {
> dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
> +}
> +
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
> b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
> new file mode 100644
> index 00000000000..3e3f9eaa65e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-maltivec -mno-vsx" } */
> +
> +/* Verify there is no ICE but one expected error message instead.  */
> +
> +#include <altivec.h>
> +
> +extern vector signed __int128 res_vslll;
> +extern unsigned long long aull[2];
> +
> +void
> +testVectorInt128Pack ()
> +{
> +  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* {
> dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
> +}
> +
> --
> 2.25.1
>
Kewen.Lin June 12, 2023, 6:48 a.m. UTC | #2 
on 2023/6/12 02:39, David Edelsohn wrote:
> On Tue, Jun 6, 2023 at 5: 19 AM Kewen. Lin <linkw@ linux. ibm. com> wrote: Hi, As PR109932 shows, builtins __builtin_{un,}pack_vector_int128 should be guarded under vsx rather than power7, as their corresponding bif patterns have the conditions
> ZjQcmQRYFpfptBannerStart
> This Message Is From an External Sender
> This message came from outside your organization.
>  
> ZjQcmQRYFpfptBannerEnd
> On Tue, Jun 6, 2023 at 5:19 AM Kewen.Lin <linkw@linux.ibm.com <mailto:linkw@linux.ibm.com>> wrote:
> 
>     Hi,
> 
>     As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
>     should be guarded under vsx rather than power7, as their
>     corresponding bif patterns have the conditions TARGET_VSX
>     and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
>     move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
>     their supports.
> 
>     Bootstrapped and regtested on powerpc64-linux-gnu P7/P8/P9 and
>     powerpc64le-linux-gnu P9 and P10.
> 
>     I'll push this next week if no objections.
> 
>     BR,
>     Kewen
>     -----
>             PR target/109932
> 
>     gcc/ChangeLog:
> 
>             * config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
>             __builtin_unpack_vector_int128): Move from stanza power7 to vsx.
> 
>     gcc/testsuite/ChangeLog:
> 
>             * gcc.target/powerpc/pr109932-1.c: New test.
>             * gcc.target/powerpc/pr109932-2.c: New test.
> 
> 
> This is okay.

Thanks David, pushed as r14-1704.  Will backport after burn-in time.

BR,
Kewen

> 
> Thanks, David
>  
> 
>     ---
>      gcc/config/rs6000/rs6000-builtins.def         | 14 +++++++-------
>      gcc/testsuite/gcc.target/powerpc/pr109932-1.c | 16 ++++++++++++++++
>      gcc/testsuite/gcc.target/powerpc/pr109932-2.c | 16 ++++++++++++++++
>      3 files changed, 39 insertions(+), 7 deletions(-)
>      create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-1.c
>      create mode 100644 gcc/testsuite/gcc.target/powerpc/pr109932-2.c
> 
>     diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
>     index 92d9b46e1b9..a38184b0ef9 100644
>     --- a/gcc/config/rs6000/rs6000-builtins.def
>     +++ b/gcc/config/rs6000/rs6000-builtins.def
>     @@ -2009,6 +2009,13 @@
>        const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
>          XXSPLTD_V2DI vsx_xxspltd_v2di {}
> 
>     +  const vsq __builtin_pack_vector_int128 (unsigned long long, \
>     +                                          unsigned long long);
>     +    PACK_V1TI packv1ti {}
>     +
>     +  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
>     +    UNPACK_V1TI unpackv1ti {}
>     +
> 
>      ; Power7 builtins (ISA 2.06).
>      [power7]
>     @@ -2030,16 +2037,9 @@
>        const unsigned int __builtin_divweu (unsigned int, unsigned int);
>          DIVWEU diveu_si {}
> 
>     -  const vsq __builtin_pack_vector_int128 (unsigned long long, \
>     -                                          unsigned long long);
>     -    PACK_V1TI packv1ti {}
>     -
>        void __builtin_ppc_speculation_barrier ();
>          SPECBARR speculation_barrier {}
> 
>     -  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
>     -    UNPACK_V1TI unpackv1ti {}
>     -
> 
>      ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
>      [power7-64]
>     diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
>     new file mode 100644
>     index 00000000000..3e3f9eaa65e
>     --- /dev/null
>     +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
>     @@ -0,0 +1,16 @@
>     +/* { dg-require-effective-target powerpc_altivec_ok } */
>     +/* { dg-options "-maltivec -mno-vsx" } */
>     +
>     +/* Verify there is no ICE but one expected error message instead.  */
>     +
>     +#include <altivec.h>
>     +
>     +extern vector signed __int128 res_vslll;
>     +extern unsigned long long aull[2];
>     +
>     +void
>     +testVectorInt128Pack ()
>     +{
>     +  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
>     +}
>     +
>     diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
>     new file mode 100644
>     index 00000000000..3e3f9eaa65e
>     --- /dev/null
>     +++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
>     @@ -0,0 +1,16 @@
>     +/* { dg-require-effective-target powerpc_altivec_ok } */
>     +/* { dg-options "-maltivec -mno-vsx" } */
>     +
>     +/* Verify there is no ICE but one expected error message instead.  */
>     +
>     +#include <altivec.h>
>     +
>     +extern vector signed __int128 res_vslll;
>     +extern unsigned long long aull[2];
>     +
>     +void
>     +testVectorInt128Pack ()
>     +{
>     +  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
>     +}
>     +
>     --
>     2.25.1
>
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 92d9b46e1b9..a38184b0ef9 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2009,6 +2009,13 @@ 
   const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
     XXSPLTD_V2DI vsx_xxspltd_v2di {}

+  const vsq __builtin_pack_vector_int128 (unsigned long long, \
+                                          unsigned long long);
+    PACK_V1TI packv1ti {}
+
+  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+    UNPACK_V1TI unpackv1ti {}
+

 ; Power7 builtins (ISA 2.06).
 [power7]
@@ -2030,16 +2037,9 @@ 
   const unsigned int __builtin_divweu (unsigned int, unsigned int);
     DIVWEU diveu_si {}

-  const vsq __builtin_pack_vector_int128 (unsigned long long, \
-                                          unsigned long long);
-    PACK_V1TI packv1ti {}
-
   void __builtin_ppc_speculation_barrier ();
     SPECBARR speculation_barrier {}

-  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
-    UNPACK_V1TI unpackv1ti {}
-

 ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
 [power7-64]
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
new file mode 100644
index 00000000000..3e3f9eaa65e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
@@ -0,0 +1,16 @@ 
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
new file mode 100644
index 00000000000..3e3f9eaa65e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
@@ -0,0 +1,16 @@ 
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+