[committed,2/6] amdgcn: Resolve insn conditions at compile time
Commit Message
GET_MODE_NUNITS isn't a compile time constant, so we end up with many
impossible insns in the machine description. Adding MODE_VF allows the insns
to be eliminated completely.
gcc/ChangeLog:
* config/gcn/gcn-valu.md
(<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>): Use MODE_VF.
(<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>): Likewise.
* config/gcn/gcn.h (MODE_VF): New macro.
---
gcc/config/gcn/gcn-valu.md | 10 ++++++----
gcc/config/gcn/gcn.h | 24 ++++++++++++++++++++++++
2 files changed, 30 insertions(+), 4 deletions(-)
@@ -2873,8 +2873,9 @@ (define_insn "<cvt_name><VCVT_MODE:mode><VCVT_FMODE:mode>2<exec>"
[(set (match_operand:VCVT_FMODE 0 "register_operand" "= v")
(cvt_op:VCVT_FMODE
(match_operand:VCVT_MODE 1 "gcn_alu_operand" "vSvB")))]
- "gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode,
- <cvt_name>_cvt)"
+ "MODE_VF (<VCVT_MODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode)
+ && gcn_valid_cvt_p (<VCVT_MODE:MODE>mode, <VCVT_FMODE:MODE>mode,
+ <cvt_name>_cvt)"
"v_cvt<cvt_operands>\t%0, %1"
[(set_attr "type" "vop1")
(set_attr "length" "8")])
@@ -2883,8 +2884,9 @@ (define_insn "<cvt_name><VCVT_FMODE:mode><VCVT_IMODE:mode>2<exec>"
[(set (match_operand:VCVT_IMODE 0 "register_operand" "= v")
(cvt_op:VCVT_IMODE
(match_operand:VCVT_FMODE 1 "gcn_alu_operand" "vSvB")))]
- "gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode,
- <cvt_name>_cvt)"
+ "MODE_VF (<VCVT_IMODE:MODE>mode) == MODE_VF (<VCVT_FMODE:MODE>mode)
+ && gcn_valid_cvt_p (<VCVT_FMODE:MODE>mode, <VCVT_IMODE:MODE>mode,
+ <cvt_name>_cvt)"
"v_cvt<cvt_operands>\t%0, %1"
[(set_attr "type" "vop1")
(set_attr "length" "8")])
@@ -678,3 +678,27 @@ enum gcn_builtin_codes
/* Trampolines */
#define TRAMPOLINE_SIZE 36
#define TRAMPOLINE_ALIGNMENT 64
+
+/* MD Optimization.
+ The following are intended to be obviously constant at compile time to
+ allow genconditions to eliminate bad patterns at compile time. */
+#define MODE_VF(M) \
+ ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \
+ || M == V64SFmode || M == V64DImode || M == V64DFmode) \
+ ? 64 \
+ : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \
+ || M == V32SFmode || M == V32DImode || M == V32DFmode) \
+ ? 32 \
+ : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \
+ || M == V16SFmode || M == V16DImode || M == V16DFmode) \
+ ? 16 \
+ : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \
+ || M == V8SFmode || M == V8DImode || M == V8DFmode) \
+ ? 8 \
+ : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \
+ || M == V4SFmode || M == V4DImode || M == V4DFmode) \
+ ? 4 \
+ : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \
+ || M == V2SFmode || M == V2DImode || M == V2DFmode) \
+ ? 2 \
+ : 1)