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[v3,7/9] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2

Message ID 0ac6b0c13cfd5465a6ce38a5f04fc172e4ffb7da.1684918169.git.jie.mei@oss.cipunited.com
State Accepted
Headers
Series MIPS: Add MIPS16e2 ASE instrucions. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

梅杰 May 24, 2023, 9:41 a.m. UTC 
  The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.

gcc/ChangeLog:

	* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
	for ISA_HAS_MIPS16E2.
	(ISA_HAS_SYNC): Same as above.
	(ISA_HAS_LL_SC): Same as above.
---
 gcc/config/mips/mips.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b6c100060da..f50b279af33 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1247,7 +1247,8 @@  struct mips_cpu_info {
 				 && !TARGET_MIPS16)
 
 /* ISA has data prefetch, LL and SC with limited 9-bit displacement.  */
-#define ISA_HAS_9BIT_DISPLACEMENT	(mips_isa_rev >= 6)
+#define ISA_HAS_9BIT_DISPLACEMENT	(mips_isa_rev >= 6		\
+					 || ISA_HAS_MIPS16E2)
 
 /* ISA has data indexed prefetch instructions.  This controls use of
    'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
@@ -1340,7 +1341,8 @@  struct mips_cpu_info {
 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
 
 /* ISA includes sync.  */
-#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16)
+#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900)	\
+		      && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
 #define GENERATE_SYNC			\
   (target_flags_explicit & MASK_LLSC	\
    ? TARGET_LLSC && !TARGET_MIPS16	\
@@ -1349,7 +1351,8 @@  struct mips_cpu_info {
 /* ISA includes ll and sc.  Note that this implies ISA_HAS_SYNC
    because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
    instructions.  */
-#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
+#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900	\
+		       && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
 #define GENERATE_LL_SC			\
   (target_flags_explicit & MASK_LLSC	\
    ? TARGET_LLSC && !TARGET_MIPS16	\