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[61.216.141.121]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a65c200b00288628acf6dsm5376875pjs.14.2024.01.07.22.15.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 07 Jan 2024 22:15:56 -0800 (PST) Message-ID: <05750a1e-8f51-4109-9342-3b0b9670cbd2@gmail.com> Date: Mon, 8 Jan 2024 14:15:54 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches , Kyrylo Tkachov , Richard Earnshaw Cc: "Jason.Wu@anshingtek.com.tw" From: Chung-Ju Wu Subject: [PATCH 1/2] arm: Add cortex-m52 core X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1787501855094901112 X-GMAIL-MSGID: 1787501855094901112 Hi, Recently, Arm announced the Cortex-M52, delivering increased performance in DSP and ML along with a range of other features and benefits. For the completeness of Arm ecosystem, we hope that cortex-m52 support could be available in gcc-14. Attached is the patch to support cortex-m52 cpu with MVE and PACBTI enabled in GCC. Bootstrapped and tested on arm-none-eabi. Is it OK for trunk? Regards, jasonwucj From d0856b516c5d270a852f3edd9df5dadccde5b94e Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Wed, 6 Dec 2023 15:49:58 +0800 Subject: [PATCH 1/2] arm: Add support for Arm Cortex-M52 CPU. This patch adds the -mcpu support for the Arm Cortex-M52 CPU which is an Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. -mcpu=cortex-m52 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. The cde feature is supported by specifying +cdecpN (e.g. -mcpu=cortex-m52+cdecp), where N is the coprocessor number 0 to 7. Also following options are provided to disable default features. +nomve.fp (disables MVE Floating point) +nomve (disables MVE Integer and MVE Floating point) +nodsp (disables dsp, MVE Integer and MVE Floating point) +nopacbti (disables pacbti) +nofp (disables floating point and MVE floating point) Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in (cortex-m52): New cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. --- gcc/config/arm/arm-cpus.in | 21 +++++++++++++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 6 +++--- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 6fa7e315ef0..451b15fe9f9 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1641,6 +1641,27 @@ begin cpu cortex-m35p costs v7m end cpu cortex-m35p +begin cpu cortex-m52 + cname cortexm52 + tune flags LDSCHED + architecture armv8.1-m.main+pacbti+mve.fp+fp.dp + option nopacbti remove pacbti + option nomve.fp remove mve_float + option nomve remove mve mve_float + option nofp remove ALL_FP mve_float + option nodsp remove MVE mve_float + option cdecp0 add cdecp0 + option cdecp1 add cdecp1 + option cdecp2 add cdecp2 + option cdecp3 add cdecp3 + option cdecp4 add cdecp4 + option cdecp5 add cdecp5 + option cdecp6 add cdecp6 + option cdecp7 add cdecp7 + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu cortex-m52 + begin cpu cortex-m55 cname cortexm55 tune flags LDSCHED diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 9d6ae875ede..d3eb9a97739 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) EnumValue Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) +EnumValue +Enum(processor_type) String(cortex-m52) Value( TARGET_CPU_cortexm52) + EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 7318f03b97e..6a631d82966 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,7 +49,7 @@ cortexa710,cortexx1,cortexx1c, neoversen1,cortexa75cortexa55,cortexa76cortexa55, neoversev1,neoversen2,cortexm23, - cortexm33,cortexm35p,cortexm55, - starmc1,cortexm85,cortexr52, - cortexr52plus" + cortexm33,cortexm35p,cortexm52, + cortexm55,starmc1,cortexm85, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)")))