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[committed] RISC-V: Adjust long unconditional branch sequence

Message ID 04984416-680a-4768-92fb-95daab4c4017@ventanamicro.com
State Unresolved
Headers
Series [committed] RISC-V: Adjust long unconditional branch sequence |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Jeff Law Oct. 11, 2023, 10:26 p.m. UTC 
  Andrew and I independently noted the long unconditional branch sequence 
was using the "call" pseudo op.  Technically it works, but it's a bit 
odd.  This patch flips it to use the "jump" pseudo-op.

This was tested with a hacked-up local compiler which forced all 
branches/jumps to be long jumps.  Naturally it triggered some failures 
for scan-asm tests but no execution regressions (which is mostly what I 
was testing for).

I've updated the long branch support item in the RISE wiki to indicate 
that we eventually want a register scavenging approach with a fallback 
to $ra in the future so that we don't muck up the return address 
predictors.  It's not super-high priority and shouldn't be terrible to 
implement given we've got the $ra fallback when a suitable register can 
not be found.


Pushed to the trunk,

Jeff
commit a3e50ee96dc3e25ca52608e58c4e653f9976cb4e
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Wed Oct 11 16:18:22 2023 -0600

    RISC-V Adjust long unconditional branch sequence
    
    Andrew and I independently noted the long unconditional branch sequence was
    using the "call" pseudo op.  Technically it works, but it's a bit odd.  This
    patch flips it to use the "jump" pseudo-op.
    
    This was tested with a hacked-up local compiler which forced all branches/jumps
    to be long jumps.  Naturally it triggered some failures for scan-asm tests but
    no execution regressions (which is mostly what I was testing for).
    
    I've updated the long branch support item in the RISE wiki to indicate that we
    eventually want a register scavenging approach with a fallback to $ra in the
    future so that we don't muck up the return address predictors.  It's not
    super-high priority and shouldn't be terrible to implement given we've got the
    $ra fallback when a suitable register can not be found.
    
    gcc/
            * config/riscv/riscv.md (jump): Adjust sequence to use a "jump"
            pseudo op instead of a "call" pseudo op.
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Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c26541bd5ce..23d91331290 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2924,7 +2924,7 @@  (define_insn "jump"
   /* Hopefully this does not happen often as this is going
      to clobber $ra and muck up the return stack predictors.  */
   if (get_attr_length (insn) == 8)
-    return "call\t%l0";
+    return "jump\t%l0,ra";
 
   return "j\t%l0";
 }