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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id x21-20020aa7d6d5000000b0051a36239e88si3753135edr.293.2023.06.19.01.33.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 01:33:31 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss.cipunited.com header.s=feishu2303200042 header.b=5GQOFmni; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B7EE33853D3C for ; Mon, 19 Jun 2023 08:32:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.18]) by sourceware.org (Postfix) with UTF8SMTPS id 180FF3858031 for ; Mon, 19 Jun 2023 08:31:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 180FF3858031 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1687163508; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=9klSIez/4D8vIRfUqtRStxIab5NIy6N7CgiDOfwh3MA=; b=5GQOFmni7Dlp8Cp7qYKHdvbtTgkbdQ5rQqD2F9S3Gj5g8+r7TatgErVh44md7TcxHGBKqM 6LdxkZSNkztcu8VDioCQqdfhqs6FpGLFYqOJdyX/XPjgUA7KXn68/DVBtGDQDsWGZpUj0s EvucIu47JQPS2BYTkBFR6YJ2eeGmasiWbrjAj/CtzJ1rndVtRJ/Ay8nMCPkgixmXoLswjU kc6BglJPePoLmVBOI5EenQWiqhE3pc3eq1ZVjY06YR9lDeiLIGRsUl9VK+cMyeC6FUz3BJ 2SChCvewwb0AG3D4JtR3NNHa05ZnfiUR5i7YpeY2czis69pZbmsLZhDLsaH9sg== Mime-Version: 1.0 X-Lms-Return-Path: To: From: "Jie Mei" Message-Id: <041a36a59f72a2b9a3f3a15f8362dffc0c3be803.1687162620.git.jie.mei@oss.cipunited.com> References: X-Mailer: git-send-email 2.40.1 Cc: "YunQiang Su" , "Maciej W . Rozycki" Subject: [PATCH v4 5/9] MIPS: Add LUI instruction for mips16e2 Date: Mon, 19 Jun 2023 16:29:54 +0800 In-Reply-To: X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, HTML_MESSAGE, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769119271168424162?= X-GMAIL-MSGID: =?utf-8?q?1769119271168424162?= This patch adds LUI instruction from mips16e2 with corresponding test. gcc/ChangeLog: * config/mips/mips.cc(mips_symbol_insns_1): Generates LUI instruction. (mips_const_insns): Same as above. (mips_output_move): Same as above. (mips_output_function_prologue): Same as above. * config/mips/mips.md: Same as above gcc/testsuite/ChangeLog: * gcc.target/mips/mips16e2.c: Add new tests for mips16e2. --- gcc/config/mips/mips.cc | 44 ++++++++++++++++++------ gcc/config/mips/mips.md | 2 +- gcc/testsuite/gcc.target/mips/mips16e2.c | 22 ++++++++++++ 3 files changed, 56 insertions(+), 12 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 33a1bada831..cdc04bec217 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -2295,7 +2295,9 @@ mips_symbol_insns_1 (enum mips_symbol_type type, machine_mode mode) The final address is then $at + %lo(symbol). With 32-bit symbols we just need a preparatory LUI for normal mode and a preparatory LI and SLL for MIPS16. */ - return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; + return ABI_HAS_64BIT_SYMBOLS + ? 6 + : (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? 3 : 2; case SYMBOL_GP_RELATIVE: /* Treat GP-relative accesses as taking a single instruction on @@ -2867,7 +2869,7 @@ mips_const_insns (rtx x) /* This is simply an LUI for normal mode. It is an extended LI followed by an extended SLL for MIPS16. */ - return TARGET_MIPS16 ? 4 : 1; + return TARGET_MIPS16 ? (ISA_HAS_MIPS16E2 ? 2 : 4) : 1; case CONST_INT: if (TARGET_MIPS16) @@ -2879,7 +2881,10 @@ mips_const_insns (rtx x) : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 : IN_RANGE (-INTVAL (x), 0, 255) ? 2 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 - : 0); + : ISA_HAS_MIPS16E2 + ? (trunc_int_for_mode (INTVAL (x), SImode) == INTVAL (x) + ? 4 : 8) + : 0); return mips_build_integer (codes, INTVAL (x)); @@ -5252,6 +5257,11 @@ mips_output_move (rtx dest, rtx src) if (!TARGET_MIPS16) return "li\t%0,%1\t\t\t# %X1"; + if (ISA_HAS_MIPS16E2 + && LUI_INT (src) + && !SMALL_OPERAND_UNSIGNED (INTVAL (src))) + return "lui\t%0,%%hi(%1)\t\t\t# %X1"; + if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) return "li\t%0,%1"; @@ -5260,7 +5270,7 @@ mips_output_move (rtx dest, rtx src) } if (src_code == HIGH) - return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; + return (TARGET_MIPS16 && !ISA_HAS_MIPS16E2) ? "#" : "lui\t%0,%h1"; if (CONST_GP_P (src)) return "move\t%0,%1"; @@ -11983,13 +11993,25 @@ mips_output_function_prologue (FILE *file) { if (TARGET_MIPS16) { - /* This is a fixed-form sequence. The position of the - first two instructions is important because of the - way _gp_disp is defined. */ - output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); - output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); - output_asm_insn ("sll\t$2,16", 0); - output_asm_insn ("addu\t$2,$3", 0); + if (ISA_HAS_MIPS16E2) + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("lui\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("addu\t$2,$3", 0); + } + else + { + /* This is a fixed-form sequence. The position of the + first two instructions is important because of the + way _gp_disp is defined. */ + output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); + output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); + output_asm_insn ("sll\t$2,16", 0); + output_asm_insn ("addu\t$2,$3", 0); + } } else { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index db11646709c..b2ab23dc931 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4634,7 +4634,7 @@ (define_split [(set (match_operand:P 0 "d_operand") (high:P (match_operand:P 1 "symbolic_operand_with_high")))] - "TARGET_MIPS16 && reload_completed" + "TARGET_MIPS16 && reload_completed && !ISA_HAS_MIPS16E2" [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c index ce8b4f1819b..780891b4056 100644 --- a/gcc/testsuite/gcc.target/mips/mips16e2.c +++ b/gcc/testsuite/gcc.target/mips/mips16e2.c @@ -100,3 +100,25 @@ test08 (unsigned int a) return ((a + 0x2) ^ 0x3f0); } +/* Test LUI. */ + +/* { dg-final { scan-assembler "test09:.*\tlui\t.*test09\n" } } */ +int +test09 (void) +{ + return 0x44440000; +} + +/* Test LUI relocation sequence chang. */ + +/* { dg-final { scan-assembler "test10:.*\tlui\t.*test10\n" } } */ +int *a10; + +int +test10 (int i) +{ + a10 = &i; + *a10 = 0x44440000; + return i; +} +