diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 7702978..846aa32 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -669,26 +669,26 @@ archs4x, archs4xd"
    || (satisfies_constraint_Cm3 (operands[1])
        && memory_operand (operands[0], QImode))"
   "@
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   ldb%? %0,%1
-   stb%? %1,%0
-   ldb%? %0,%1
-   xldb%U1 %0,%1
-   ldb%U1%V1 %0,%1
-   xstb%U0 %1,%0
-   stb%U0%V0 %1,%0
-   stb%U0%V0 %1,%0
-   stb%U0%V0 %1,%0
-   stb%U0%V0 %1,%0"
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   ldb%?\\t%0,%1
+   stb%?\\t%1,%0
+   ldb%?\\t%0,%1
+   xldb%U1\\t%0,%1
+   ldb%U1%V1\\t%0,%1
+   xstb%U0\\t%1,%0
+   stb%U0%V0\\t%1,%0
+   stb%U0%V0\\t%1,%0
+   stb%U0%V0\\t%1,%0
+   stb%U0%V0\\t%1,%0"
   [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,load,store,load,load,load,store,store,store,store,store")
    (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,false,true,true,true,false,false,false,false,false,false,false")
    (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,no,no,no,no,no,no,no,no,no,no")
@@ -713,26 +713,26 @@ archs4x, archs4xd"
    || (satisfies_constraint_Cm3 (operands[1])
        && memory_operand (operands[0], HImode))"
   "@
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1
-   ld%_%? %0,%1
-   st%_%? %1,%0
-   xld%_%U1 %0,%1
-   ld%_%U1%V1 %0,%1
-   xst%_%U0 %1,%0
-   st%_%U0%V0 %1,%0
-   st%_%U0%V0 %1,%0
-   st%_%U0%V0 %1,%0
-   st%_%U0%V0 %1,%0"
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1
+   ld%_%?\\t%0,%1
+   st%_%?\\t%1,%0
+   xld%_%U1\\t%0,%1
+   ld%_%U1%V1\\t%0,%1
+   xst%_%U0\\t%1,%0
+   st%_%U0%V0\\t%1,%0
+   st%_%U0%V0\\t%1,%0
+   st%_%U0%V0\\t%1,%0
+   st%_%U0%V0\\t%1,%0"
   [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,move,load,store,load,load,store,store,store,store,store")
    (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,maybe_limm,false,true,true,false,false,false,false,false,false,false")
    (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,yes,no,no,no,no,no,no,no,no,no")
@@ -818,7 +818,7 @@ archs4x, archs4xd"
 		  (plus:SI (reg:SI SP_REG)
 			   (match_operand 1 "immediate_operand" "Cal")))))]
   "reload_completed"
-  "ld.a %0,[sp,%1]"
+  "ld.a\\t%0,[sp,%1]"
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
@@ -830,7 +830,7 @@ archs4x, archs4xd"
       (unspec:SI [(match_operand:SI 1 "register_operand" "c")]
        UNSPEC_ARC_DIRECT))]
   ""
-  "st%U0 %1,%0\;st%U0.di %1,%0"
+  "st%U0\\t%1,%0\;st%U0.di\\t%1,%0"
   [(set_attr "type" "store")])
 
 ;; Combiner patterns for compare with zero
@@ -944,7 +944,7 @@ archs4x, archs4xd"
    (set (match_operand:SI 0 "register_operand" "=w")
 	(match_dup 3))]
   ""
-  "%O3.f %0,%1"
+  "%O3.f\\t%0,%1"
   [(set_attr "type" "compare")
    (set_attr "cond" "set_zn")
    (set_attr "length" "4")])
@@ -987,15 +987,15 @@ archs4x, archs4xd"
     switch (which_alternative)
     {
     case 0: case 2: case 3: case 7:
-      return \"tst%? %1,%2\";
+      return \"tst%?\\t%1,%2\";
     case 1:
-      return \"btst%? %1,%z2\";
+      return \"btst%?\\t%1,%z2\";
     case 4:
-      return \"bmsk%?.f 0,%1,%Z2\";
+      return \"bmsk%?.f\\t0,%1,%Z2\";
     case 5:
-      return \"bclr%?.f 0,%1,%M2\";
+      return \"bclr%?.f\\t0,%1,%M2\";
     case 6:
-      return \"asr.f 0,%1,%p2\";
+      return \"asr.f\\t0,%1,%p2\";
     default:
       gcc_unreachable ();
     }
@@ -1026,7 +1026,7 @@ archs4x, archs4xd"
    && (INTVAL (operands[3]) + INTVAL (operands[2]) <= 11
        || (INTVAL (operands[3]) <= 11
 	   && INTVAL (operands[3]) + INTVAL (operands[2]) == 32))"
-  "tst %1,((1<<%2)-1)<<%3"
+  "tst\\t%1,((1<<%2)-1)<<%3"
   [(set_attr "type" "compare")
    (set_attr "cond" "set_zn")
    (set_attr "length" "4")])
@@ -1058,11 +1058,11 @@ archs4x, archs4xd"
    (clobber (match_scratch:SI 4 "=X,X,X,Rrq,X"))]
   ""
   "@
-   btst%? %1,%3
-   btst %1,%3
-   bmsk.f 0,%1,%2-1
-   movb.f.cl %4,%1,%3,%3,%2
-   and.f 0,%1,((1<<%2)-1)<<%3"
+   btst%?\\t%1,%3
+   btst\\t%1,%3
+   bmsk.f\\t0,%1,%2-1
+   movb.f.cl\\t%4,%1,%3,%3,%2
+   and.f\\t0,%1,((1<<%2)-1)<<%3"
   [(set_attr "iscompact" "maybe,false,false,false,false")
    (set_attr "type" "compare,compare,compare,shift,compare")
    (set_attr "cond" "set_zn")
@@ -1146,7 +1146,7 @@ archs4x, archs4xd"
    (set (match_operand:SI 0 "register_operand" "=w,w,w")
 	(match_dup 4))]
   ""
-  "%O4.f %0,%1,%2 ; non-mult commutative"
+  "%O4.f\\t%0,%1,%2 ; non-mult commutative"
   [(set_attr "type" "compare,compare,compare")
    (set_attr "cond" "set_zn,set_zn,set_zn")
    (set_attr "length" "4,4,8")])
@@ -1164,7 +1164,7 @@ archs4x, archs4xd"
    (set (match_operand:SI 0 "register_operand" "=W,W,W")
 	(match_dup 4))]
   "!TARGET_ARC600_FAMILY"
-  "%O4.f %0,%1,%2 ; mult commutative"
+  "%O4.f\\t%0,%1,%2 ; mult commutative"
   [(set_attr "type" "compare,compare,compare")
    (set_attr "cond" "set_zn,set_zn,set_zn")
    (set_attr "length" "4,4,8")])
@@ -1248,7 +1248,7 @@ archs4x, archs4xd"
    (set (match_operand:SI 0 "register_operand" "=w,w,w")
 	(and:SI (match_dup 1) (not:SI (match_dup 2))))]
   ""
-  "bic.f %0,%1,%2"
+  "bic.f\\t%0,%1,%2"
   [(set_attr "type" "compare,compare,compare")
    (set_attr "cond" "set_zn,set_zn,set_zn")
    (set_attr "length" "4,4,8")])
@@ -1640,13 +1640,13 @@ archs4x, archs4xd"
 {
   if (rtx_equal_p (operands[1], const0_rtx) && GET_CODE (operands[3]) == NE
       && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11))
-    return "sub%?.ne %0,%0,%0";
+    return "sub%?.ne\\t%0,%0,%0";
   /* ??? might be good for speed on ARC600 too, *if* properly scheduled.  */
   if ((optimize_size && (!TARGET_ARC600_FAMILY))
       && rtx_equal_p (operands[1], constm1_rtx)
       && GET_CODE (operands[3]) == LTU)
-    return "sbc.cs %0,%0,%0";
-  return "mov.%d3 %0,%1";
+    return "sbc.cs\\t%0,%0,%0";
+  return "mov.%d3\\t%0,%1";
 }
   [(set_attr "type" "cmove,cmove")
    (set_attr "length" "4,8")])
@@ -1734,11 +1734,11 @@ archs4x, archs4xd"
  	 the first register operand 0 is the same as the second register of
  	 operand 1, we must copy in the opposite order.  */
        if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
- 	return \"mov.%d3 %R0,%R1\;mov.%d3 %0,%1\";
+ 	return \"mov.%d3\\t%R0,%R1\;mov.%d3\\t%0,%1\";
        else
- 	return \"mov.%d3 %0,%1\;mov.%d3 %R0,%R1\";
+ 	return \"mov.%d3\\t%0,%1\;mov.%d3\\t%R0,%R1\";
      case 1 :
-	return \"mov.%d3 %L0,%L1\;mov.%d3 %H0,%H1\";
+	return \"mov.%d3\\t%L0,%L1\;mov.%d3\\t%H0,%H1\";
 
 
      }
@@ -1755,8 +1755,8 @@ archs4x, archs4xd"
 		      (match_operand:SF 2 "register_operand" "0,0")))]
   ""
   "@
-   mov.%d3 %0,%1
-   mov.%d3 %0,%1 ; %A1"
+   mov.%d3\\t%0,%1
+   mov.%d3\\t%0,%1 ; %A1"
   [(set_attr "type" "cmove,cmove")])
 
 (define_insn "*movdfcc_insn"
@@ -1776,12 +1776,11 @@ archs4x, archs4xd"
 	 the first register operand 0 is the same as the second register of
 	 operand 1, we must copy in the opposite order.  */
       if (REGNO (operands[0]) == REGNO (operands[2]) + 1)
-	return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\";
+	return \"mov.%d1\\t%R0,%R2\;mov.%d1\\t%0,%2\";
       else
-	return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\";
+	return \"mov.%d1\\t%0,%2\;mov.%d1\\t%R0,%R2\";
     case 1 :
-	      return \"mov.%d1 %L0,%L2\;mov.%d1 %H0,%H2; %A2 \";
-
+      return \"mov.%d1\\t%L0,%L2\;mov.%d1\\t%H0,%H2; %A2\";
     }
 }"
   [(set_attr "type" "cmove,cmove")
@@ -1944,7 +1943,7 @@ archs4x, archs4xd"
   [(set (match_operand:SI 0 "dest_reg_operand" "=q,w,w")
 	(abs:SI (match_operand:SI 1 "nonmemory_operand" "q,cL,Cal")))]
   ""
-  "abs%? %0,%1"
+  "abs%?\\t%0,%1"
   [(set_attr "type" "two_cycle_core")
    (set_attr "length" "*,4,8")
    (set_attr "iscompact" "true,false,false")])
@@ -2031,7 +2030,7 @@ archs4x, archs4xd"
 	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,r,0,  0,  r"))
 		 (match_operand:HI 2 "short_const_int_operand"          "L,L,I,C16,C16")))]
   "TARGET_MPYW"
-  "mpyw%? %0,%1,%2"
+  "mpyw%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "mul16_em")
@@ -2044,7 +2043,7 @@ archs4x, archs4xd"
 	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"  "0,0,r"))
 		 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" "q,r,r"))))]
   "TARGET_MPYW"
-  "mpyw%? %0,%1,%2"
+  "mpyw%?\\t%0,%1,%2"
   [(set_attr "length" "*,4,4")
    (set_attr "iscompact" "maybe,false,false")
    (set_attr "type" "mul16_em")
@@ -2071,7 +2070,7 @@ archs4x, archs4xd"
 	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, r,  0,  0,  r"))
 		 (match_operand:HI 2 "short_unsigned_const_operand"     " L, L,J12,J16,J16")))]
   "TARGET_MPYW"
-  "mpyuw%? %0,%1,%2"
+  "mpyuw%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "mul16_em")
@@ -2084,7 +2083,7 @@ archs4x, archs4xd"
 	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, 0, r"))
 		 (zero_extend:SI (match_operand:HI 2 "register_operand"  "q, r, r"))))]
   "TARGET_MPYW"
-  "mpyuw%? %0,%1,%2"
+  "mpyuw%?\\t%0,%1,%2"
   [(set_attr "length" "*,4,4")
    (set_attr "iscompact" "maybe,false,false")
    (set_attr "type" "mul16_em")
@@ -2155,7 +2154,7 @@ archs4x, archs4xd"
 				  (const_int 0))))
    (clobber (match_operand:SI 3 "acc1_operand" ""))]
   "TARGET_MULMAC_32BY16_SET"
-  "mululw 0, %0, %1"
+  "mululw\\t0,%0,%1"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600")
    (set_attr "predicable" "no")
@@ -2173,7 +2172,7 @@ archs4x, archs4xd"
 	  (match_dup 2)))
    (clobber (match_operand:SI 3 "acc1_operand" ""))]
   "TARGET_MULMAC_32BY16_SET"
-  "machlw%? 0, %0, %1"
+  "machlw%?\\t0,%0,%1"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600, mulmac_600, mulmac_600")
    (set_attr "predicable" "no, no, yes")
@@ -2242,7 +2241,7 @@ archs4x, archs4xd"
 	 (sign_extend:DI (match_operand:SI 0 "register_operand" "%q, c,c,  c"))
 	 (sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "q,cL,L,C32"))))]
   "TARGET_MUL64_SET"
-  "mul64%? \t0, %0, %1"
+  "mul64%?\\t0,%0,%1"
   [(set_attr "length" "*,4,4,8")
    (set_attr "iscompact" "maybe,false,false,false")
    (set_attr "type" "multi,multi,multi,multi")
@@ -2277,7 +2276,7 @@ archs4x, archs4xd"
 	 (zero_extend:DI (match_operand:SI 0 "register_operand"  "%c,c,c"))
 	 (zero_extend:DI (match_operand:SI 1 "nonmemory_operand" "cL,L,C32"))))]
   "TARGET_MUL64_SET"
-  "mulu64%? \t0, %0, %1"
+  "mulu64%?\\t0,%0,%1"
   [(set_attr "length" "4,4,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "umulti")
@@ -2401,7 +2400,7 @@ archs4x, archs4xd"
 				  (const_int 0))))
   ]
   "TARGET_MULMAC_32BY16_SET"
-  "mullw%? 0, %0, %1"
+  "mullw%?\\t0,%0,%1"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600")
    (set_attr "predicable" "no,no,yes")
@@ -2429,7 +2428,7 @@ archs4x, archs4xd"
 	    (reg:DI MUL32x16_REG))
 	  (const_int 32) (const_int 32)))]
   "TARGET_MULMAC_32BY16_SET"
-  "machlw%? %0, %1, %2"
+  "machlw%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600")
    (set_attr "predicable" "no,no,yes")
@@ -2616,7 +2615,7 @@ archs4x, archs4xd"
 				  (const_int 0))))
   ]
   "TARGET_MULMAC_32BY16_SET"
-  "mululw 0, %0, %1"
+  "mululw\\t0,%0,%1"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600")
    (set_attr "predicable" "no")
@@ -2643,7 +2642,7 @@ archs4x, archs4xd"
 	    (reg:DI MUL32x16_REG))
 	  (const_int 32) (const_int 32)))]
   "TARGET_MULMAC_32BY16_SET"
-  "machulw%? %0, %1, %2"
+  "machulw%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "mulmac_600")
    (set_attr "predicable" "no,no,yes")
@@ -2824,7 +2823,7 @@ archs4x, archs4xd"
 ;	(plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
 ;		 (match_operand:SI 1 "register_operand" "c")))]
 ;  ""
-;  "adc %0,%1,0"
+;  "adc\\t%0,%1,0"
 ;  [(set_attr "cond" "use")
 ;   (set_attr "type" "cc_arith")
 ;   (set_attr "length" "4")])
@@ -2930,7 +2929,7 @@ archs4x, archs4xd"
 		  (ltu:SI (match_operand:CC_C 2 "cc_use_register")
 			  (const_int 0))))]
   ""
-  "sbc %0,%1,0"
+  "sbc\\t%0,%1,0"
   [(set_attr "cond" "use")
    (set_attr "type" "cc_arith")
    (set_attr "length" "4")])
@@ -3177,38 +3176,38 @@ archs4x, archs4xd"
   switch (which_alternative)
     {
     case 0: case 5: case 10: case 11: case 16: case 17: case 18:
-      return "and%? %0,%1,%2";
+      return "and%?\\t%0,%1,%2";
     case 1: case 6:
-      return "and%? %0,%2,%1";
+      return "and%?\\t%0,%2,%1";
     case 2:
-      return "bmsk%? %0,%1,%Z2";
+      return "bmsk%?\\t%0,%1,%Z2";
     case 7: case 12:
      if (satisfies_constraint_C2p (operands[2]))
        {
 	operands[2] = GEN_INT ((~INTVAL (operands[2])));
-	return "bmskn%? %0,%1,%Z2";
+	return "bmskn%?\\t%0,%1,%Z2";
        }
      else
        {
-	return "bmsk%? %0,%1,%Z2";
+	return "bmsk%?\\t%0,%1,%Z2";
        }
     case 3: case 8: case 13:
-      return "bclr%? %0,%1,%M2";
+      return "bclr%?\\t%0,%1,%M2";
     case 4:
       return (INTVAL (operands[2]) == 0xff
-	      ? "extb%? %0,%1" : "ext%_%? %0,%1");
-    case 9: case 14: return \"bic%? %0,%1,%n2-1\";
+	      ? "extb%?\\t%0,%1" : "ext%_%?\\t%0,%1");
+    case 9: case 14: return \"bic%?\\t%0,%1,%n2-1\";
     case 15:
-      return "movb.cl %0,%1,%p2,%p2,%x2";
+      return "movb.cl\\t%0,%1,%p2,%p2,%x2";
 
     case 19:
       const char *tmpl;
 
       if (satisfies_constraint_Ucm (operands[1]))
 	tmpl = (INTVAL (operands[2]) == 0xff
-		? "xldb%U1 %0,%1" : "xld%_%U1 %0,%1");
+		? "xldb%U1\\t%0,%1" : "xld%_%U1\\t%0,%1");
       else
-	tmpl = INTVAL (operands[2]) == 0xff ? "ldb %0,%1" : "ld%_ %0,%1";
+	tmpl = INTVAL (operands[2]) == 0xff ? "ldb\\t%0,%1" : "ld%_\\t%0,%1";
 
       if (TARGET_BIG_ENDIAN)
 	{
@@ -3254,7 +3253,7 @@ archs4x, archs4xd"
  		(match_operand:SI 2 "nonmemory_operand" "0,0,0,0,r,r,Cal")))]
   ""
   "@
-   bic%?\\t%0, %2, %1 ;;constraint 0
+   bic%?\\t%0,%2,%1  ;;constraint 0
    bic%?\\t%0,%2,%1  ;;constraint 1
    bic\\t%0,%2,%1    ;;constraint 2, FIXME: will it ever get generated ???
    bic%?\\t%0,%2,%1  ;;constraint 3, FIXME: will it ever get generated ???
@@ -3337,7 +3336,7 @@ archs4x, archs4xd"
   [(set (match_operand:SI 0 "dest_reg_operand" "=q,w")
 	(not:SI (match_operand:SI 1 "register_operand" "q,c")))]
   ""
-  "not%? %0,%1"
+  "not%?\\t%0,%1"
   [(set_attr "type" "unary,unary")
    (set_attr "iscompact" "true,false")])
 
@@ -3599,7 +3598,7 @@ archs4x, archs4xd"
 	(compare:CC (match_operand:SI 0 "register_operand"   "q, q,  h, c, c,  q,c")
 		    (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,cL,Cal,Cal")))]
   ""
-  "cmp%? %0,%B1"
+  "cmp%?\\t%0,%B1"
   [(set_attr "type" "compare")
    (set_attr "iscompact" "true,true,true,false,false,true_limm,false")
    (set_attr "predicable" "no,no,no,no,yes,no,yes")
@@ -3612,7 +3611,7 @@ archs4x, archs4xd"
 	(compare:CC_ZN (match_operand:SI 0 "register_operand"  "q,c")
 		       (const_int 0)))]
   ""
-  "tst%? %0,%0"
+  "tst%?\\t%0,%0"
   [(set_attr "type" "compare,compare")
    (set_attr "iscompact" "true,false")
    (set_attr "predicable" "no,yes")
@@ -3628,7 +3627,7 @@ archs4x, archs4xd"
 			   (match_operand:SI 1 "nonmemory_operand" "L,Lc"))
 	  (const_int 0)))]
   ""
-  "btst%? %0,%1"
+  "btst%?\\t%0,%1"
   [(set_attr "iscompact" "true,false")
    (set_attr "predicable" "no,yes")
    (set_attr "cond" "set")
@@ -3641,8 +3640,8 @@ archs4x, archs4xd"
 		      (match_operand:SI 1 "p2_immediate_operand"  "O,n")))]
   ""
   "@
-	cmp%? %0,%1
-	bxor.f 0,%0,%z1"
+	cmp%?\\t%0,%1
+	bxor.f\\t0,%0,%z1"
   [(set_attr "type" "compare,compare")
    (set_attr "iscompact" "true,false")
    (set_attr "cond" "set,set_zn")
@@ -3653,7 +3652,7 @@ archs4x, archs4xd"
 	(compare:CC_C (match_operand:SI 0 "register_operand"   "q, q,  h, c,  q,  c")
 		      (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,Cal,Cal")))]
   ""
-  "cmp%? %0,%1"
+  "cmp%?\\t%0,%1"
   [(set_attr "type" "compare")
    (set_attr "iscompact" "true,true,true,false,true_limm,false")
    (set_attr "cond" "set")
@@ -3763,7 +3762,7 @@ archs4x, archs4xd"
      (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
 	  (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))]
   ""
-  "mov.%d3 %0,%1"
+  "mov.%d3\\t%0,%1"
   [(set_attr "type" "cmove")
    (set_attr "length" "4,8")])
 
@@ -3799,9 +3798,9 @@ archs4x, archs4xd"
 		    (match_operand:SI 2 "nonmemory_operand" "cL,0,0"))))]
   ""
   "@
-	sub.%d4 %0,%1,%2
-	rsub.%d4 %0,%2,%1
-	rsub.%d4 %0,%2,%1"
+	sub.%d4\\t%0,%1,%2
+	rsub.%d4\\t%0,%2,%1
+	rsub.%d4\\t%0,%2,%1"
   [(set_attr "cond" "use")
    (set_attr "type" "cmove")
    (set_attr "length" "4,4,8")])
@@ -3815,7 +3814,7 @@ archs4x, archs4xd"
 	    [(match_operand:SI 1 "register_operand" "0,0")
 	     (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])))]
   ""
-  "%O3.%d5 %0,%1,%2"
+  "%O3.%d5\\t%0,%1,%2"
   [(set_attr "cond" "use")
    (set_attr "type" "cmove")
    (set_attr "length" "4,8")])
@@ -3954,11 +3953,11 @@ archs4x, archs4xd"
   [(set (pc) (match_operand:SI 0 "nonmemory_operand" "L,I,Cal,q,r"))]
   ""
   "@
-   j%!%* %0
-   j%!%* %0
-   j%!%* %0
-   j%!%* [%0]
-   j%!%* [%0]"
+   j%!%*\\t%0
+   j%!%*\\t%0
+   j%!%*\\t%0
+   j%!%*\\t[%0]
+   j%!%*\\t[%0]"
   [(set_attr "type" "jump")
    (set_attr "iscompact" "false,false,false,maybe,false")
    (set_attr "cond" "canuse,canuse_limm,canuse,canuse,canuse")])
@@ -4122,15 +4121,15 @@ archs4x, archs4xd"
    (clobber (reg:SI 31))]
   ""
   "@
-   jl%!%* [%0]
-   jl%!%* [%0]
-   jli_s %J0
-   sjli  %J0
-   bl%!%* %P0
-   bl%!%* %P0
-   jl%!%* %0
-   jl%* %0
-   jl%! %0"
+   jl%!%*\\t[%0]
+   jl%!%*\\t[%0]
+   jli_s\\t%J0
+   sjli\\t%J0
+   bl%!%*\\t%P0
+   bl%!%*\\t%P0
+   jl%!%*\\t%0
+   jl%*\\t%0
+   jl%!\\t%0"
   [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot")
    (set_attr "iscompact" "maybe,*,true,*,*,*,*,*,*")
    (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes")
@@ -4166,15 +4165,15 @@ archs4x, archs4xd"
    (clobber (reg:SI 31))]
   ""
   "@
-   jl%!%* [%1]
-   jl%!%* [%1]
-   jli_s %J1
-   sjli  %J1
-   bl%!%* %P1;1
-   bl%!%* %P1;1
-   jl%!%* %1
-   jl%* %1
-   jl%! %1"
+   jl%!%*\\t[%1]
+   jl%!%*\\t[%1]
+   jli_s\\t%J1
+   sjli\\t%J1
+   bl%!%*\\t%P1;1
+   bl%!%*\\t%P1;1
+   jl%!%*\\t%1
+   jl%*\\t%1
+   jl%!\\t%1"
   [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot")
    (set_attr "iscompact" "maybe,*,true,false,*,*,*,*,*")
    (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes")
@@ -4392,8 +4391,8 @@ archs4x, archs4xd"
 	  (clrsb:HI (match_operand:HI 1 "general_operand" "cL,Cal"))))]
   "TARGET_NORM"
   "@
-   norm%_ \t%0, %1
-   norm%_ \t%0, %1"
+   norm%_\\t%0,%1
+   norm%_\\t%0,%1"
   [(set_attr "length" "4,8")
    (set_attr "type" "two_cycle_core,two_cycle_core")])
 
@@ -4496,9 +4495,9 @@ archs4x, archs4xd"
 			    UNSPEC_ARC_SWAP))]
   "TARGET_SWAP"
   "@
-   swap \t%0, %1
-   swap \t%0, %1
-   swap \t%0, %1"
+   swap\\t%0,%1
+   swap\\t%0,%1
+   swap\\t%0,%1"
   [(set_attr "length" "4,8,4")
    (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")])
 
@@ -4509,9 +4508,9 @@ archs4x, archs4xd"
 					   UNSPEC_ARC_DIVAW))]
   "TARGET_ARC700 || TARGET_EA_SET"
   "@
-   divaw \t%0, %1, %2
-   divaw \t%0, %1, %2
-   divaw \t%0, %1, %2"
+   divaw\\t%0,%1,%2
+   divaw\\t%0,%1,%2
+   divaw\\t%0,%1,%2"
   [(set_attr "length" "4,8,8")
    (set_attr "type" "divaw,divaw,divaw")])
 
@@ -4520,9 +4519,9 @@ archs4x, archs4xd"
 		   VUNSPEC_ARC_FLAG)]
   ""
   "@
-    flag%? %0
-    flag %0
-    flag%? %0"
+    flag%?\\t%0
+    flag\\t%0
+    flag%?\\t%0"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "misc,misc,misc")
    (set_attr "predicable" "yes,no,yes")
@@ -4572,7 +4571,7 @@ archs4x, archs4xd"
   [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")]
 		   VUNSPEC_ARC_SLEEP)]
   ""
-  "sleep %0"
+  "sleep\\t%0"
   [(set_attr "length" "4")
   (set_attr "type" "misc")])
 
@@ -4596,8 +4595,8 @@ archs4x, archs4xd"
   ""
   "*
     if (check_if_valid_regno_const (operands, 1))
-      return \"mov \tr%1, %0\";
-    return \"mov \tr%1, %0\";
+      return \"mov\\tr%1,%0\";
+    return \"mov\\tr%1,%0\";
   "
   [(set_attr "length" "4")
    (set_attr "type" "unary")])
@@ -4685,7 +4684,7 @@ archs4x, archs4xd"
 {
   if (which_alternative == 0)
     {
-      return \"trap_s %0\";
+      return \"trap_s\\t%0\";
     }
 
   /* Keep this message in sync with the one in arc.cc:arc_expand_builtin,
@@ -4890,7 +4889,7 @@ archs4x, archs4xd"
 		 return \"br%d0%*\\t%1,%B2,%l3\";
        /* FALLTHRU */
        case 6: case 10:
-       case 12:return \"cmp%? %1, %B2\\n\\tb%d0%*\\t%l3 ;br%d0 out of range\";
+       case 12:return \"cmp%?\\t%1,%B2\\n\\tb%d0%*\\t%l3 ;br%d0 out of range\";
        default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length (insn)); fflush (stderr); gcc_unreachable ();
      }
    "
@@ -4952,9 +4951,9 @@ archs4x, archs4xd"
   switch (get_attr_length (insn))
     {
       case 4: return (GET_CODE (operands[3]) == EQ
-		      ? \"bbit0%* %1,%2,%0\" : \"bbit1%* %1,%2,%0\");
+		      ? \"bbit0%*\\t%1,%2,%0\" : \"bbit1%*\\t%1,%2,%0\");
       case 6:
-      case 8: return \"btst%? %1,%2\n\tb%d3%* %0; bbit out of range\";
+      case 8: return \"btst%?\\t%1,%2\n\tb%d3%*\\t%0; bbit out of range\";
       default: gcc_unreachable ();
     }
 }
@@ -5251,7 +5250,7 @@ archs4x, archs4xd"
   [(set (match_operand:SI 0 "register_operand"           "= r,r")
 	(bswap:SI (match_operand:SI 1 "nonmemory_operand" "rL,Cal")))]
   "TARGET_V2 && TARGET_SWAP"
-  "swape %0, %1"
+  "swape\\t%0,%1"
   [(set_attr "length" "4,8")
    (set_attr "type" "two_cycle_core")])
 
@@ -5284,9 +5283,9 @@ archs4x, archs4xd"
   "TARGET_HS"
   {
    if (INTVAL (operands[2]))
-      return "prefetchw [%0, %1]";
+      return "prefetchw\\t[%0, %1]";
    else
-      return "prefetch [%0, %1]";
+      return "prefetch\\t[%0, %1]";
   }
   [(set_attr "type" "load")
    (set_attr "length" "4,4,8")])
@@ -5299,9 +5298,9 @@ archs4x, archs4xd"
   {
    operands[0] = gen_rtx_MEM (SImode, operands[0]);
    if (INTVAL (operands[1]))
-      return "prefetchw%U0 %0";
+      return "prefetchw%U0\\t%0";
    else
-      return "prefetch%U0 %0";
+      return "prefetch%U0\\t%0";
    }
   [(set_attr "type" "load")
    (set_attr "length" "8")])
@@ -5311,7 +5310,7 @@ archs4x, archs4xd"
 	(div:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0,  0,  r")
 		(match_operand:SI 2 "nonmemory_operand" "r,r,  r,L,L,I,Cal,Cal")))]
   "TARGET_DIVREM"
-  "div%? %0, %1, %2"
+  "div%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "div_rem")
@@ -5324,7 +5323,7 @@ archs4x, archs4xd"
 	(udiv:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0,  0,  r")
 		 (match_operand:SI 2 "nonmemory_operand" "r,r,  r,L,L,I,Cal,Cal")))]
   "TARGET_DIVREM"
-  "divu%? %0, %1, %2"
+  "divu%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "div_rem")
@@ -5337,7 +5336,7 @@ archs4x, archs4xd"
 	(mod:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0,  0,  r")
 		(match_operand:SI 2 "nonmemory_operand" "r,r,  r,L,L,I,Cal,Cal")))]
   "TARGET_DIVREM"
-  "rem%? %0, %1, %2"
+  "rem%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "div_rem")
@@ -5350,7 +5349,7 @@ archs4x, archs4xd"
 	(umod:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0,  0,  r")
 		 (match_operand:SI 2 "nonmemory_operand" "r,r,  r,L,L,I,Cal,Cal")))]
   "TARGET_DIVREM"
-  "remu%? %0, %1, %2"
+  "remu%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "div_rem")
@@ -5366,7 +5365,7 @@ archs4x, archs4xd"
 	(arcCC_cond:SI (match_operand:SI 1 "register_operand"  "0,r,0,r,0,0,r")
 		       (match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I,n,n")))]
   "TARGET_V2 && TARGET_CODE_DENSITY"
-  "set<code>%? %0, %1, %2"
+  "set<code>%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "compare")
@@ -5379,7 +5378,7 @@ archs4x, archs4xd"
 	(ltu:SI (match_operand:SI 1 "register_operand"  "0,r,0,r,0,  0,  r")
 		(match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I,  n,  n")))]
   "TARGET_V2 && TARGET_CODE_DENSITY"
-  "setlo%? %0, %1, %2"
+  "setlo%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "compare")
@@ -5392,7 +5391,7 @@ archs4x, archs4xd"
 	(geu:SI (match_operand:SI 1 "register_operand"  "0,r,0,r,0,  0,  r")
 		(match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I,  n,  n")))]
   "TARGET_V2 && TARGET_CODE_DENSITY"
-  "seths%? %0, %1, %2"
+  "seths%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,4,4,4,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "compare")
@@ -5406,7 +5405,7 @@ archs4x, archs4xd"
 	(gtu:SI (match_operand:SI 1 "register_operand"  "r,r,  r,r")
 		(match_operand:SI 2 "nonmemory_operand" "0,r,C62,n")))]
   "TARGET_V2 && TARGET_CODE_DENSITY"
-  "setlo%? %0, %2, %1"
+  "setlo%?\\t%0,%2,%1"
   "reload_completed
    && CONST_INT_P (operands[2])
    && satisfies_constraint_C62 (operands[2])"
@@ -5429,7 +5428,7 @@ archs4x, archs4xd"
 	(leu:SI (match_operand:SI 1 "register_operand"  "r,r,  r,r")
 		(match_operand:SI 2 "nonmemory_operand" "0,r,C62,n")))]
   "TARGET_V2 && TARGET_CODE_DENSITY"
-  "seths%? %0, %2, %1"
+  "seths%?\\t%0,%2,%1"
   "reload_completed
    && CONST_INT_P (operands[2])
    && satisfies_constraint_C62 (operands[2])"
@@ -5492,9 +5491,9 @@ archs4x, archs4xd"
 		   VUNSPEC_ARC_KFLAG)]
   "TARGET_V2"
   "@
-    kflag%? %0
-    kflag %0
-    kflag%? %0"
+    kflag%?\\t%0
+    kflag\\t%0
+    kflag%?\\t%0"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "misc,misc,misc")
    (set_attr "predicable" "yes,no,yes")
@@ -5505,7 +5504,7 @@ archs4x, archs4xd"
 	(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "N")]
 			    VUNSPEC_ARC_CLRI))]
   "TARGET_V2"
-  "clri  %0"
+  "clri\\t%0"
   [(set_attr "length" "4")
    (set_attr "type" "misc")])
 
@@ -5767,7 +5766,7 @@ archs4x, archs4xd"
 			 (match_operand:SI 2 "const_int_operand" "n")
 			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32"
-  "movb.cl %0,%1,0,%3,%2"
+  "movb.cl\\t%0,%1,0,%3,%2"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5793,8 +5792,8 @@ archs4x, archs4xd"
    && (register_operand (operands[3], SImode)
        || satisfies_constraint_C18 (operands[1]))"
   "@
-   movbi %0,%0,%3,%2,%1
-   movb %0,%0,%3,%2,0,%1"
+   movbi\\t%0,%0,%3,%2,%1
+   movb\\t%0,%0,%3,%2,0,%1"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5806,7 +5805,7 @@ archs4x, archs4xd"
 			 (match_dup 1)
 			 (match_operand:SI 4 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS"
-  "movb %0,%0,%3,%2,%4,%1"
+  "movb\\t%0,%0,%3,%2,%4,%1"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5818,7 +5817,7 @@ archs4x, archs4xd"
 			 (match_dup 1)
 			 (match_operand:SI 4 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS"
-  "movb %0,%0,%3,%2,%4,%1"
+  "movb\\t%0,%0,%3,%2,%4,%1"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5830,7 +5829,7 @@ archs4x, archs4xd"
 		     (match_operand:SI 4 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS
    && INTVAL (operands[4]) + INTVAL (operands[1]) <= 32"
-  "movb %0,%0,%3,%2,%4,%1"
+  "movb\\t%0,%0,%3,%2,%4,%1"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5845,7 +5844,7 @@ archs4x, archs4xd"
 		     (match_operand:SI 4 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS
    && INTVAL (operands[4]) + INTVAL (operands[1]) <= 32"
-  "movb %0,%0,%3,%2,%4,%1"
+  "movb\\t%0,%0,%3,%2,%4,%1"
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
@@ -5876,7 +5875,7 @@ archs4x, archs4xd"
 			 (match_operand:SI 7 "const_int_operand" "n")))]
   "TARGET_NPS_BITOPS"
 {
-  output_asm_insn ("mrgb %0,%0,%6,%2,%3,%1,%5,%7,%4", operands);
+  output_asm_insn ("mrgb\\t%0,%0,%6,%2,%3,%1,%5,%7,%4", operands);
   /* The ;%? updates the known unalignment.  */
   return arc_short_long (insn, ";%?", "nop_s");
 }
@@ -5995,7 +5994,7 @@ archs4x, archs4xd"
 	(ashift:SI (match_operand:SI 1 "register_operand" "q,c")
 		   (const_int 1)))]
   ""
-  "asl%? %0,%1"
+  "asl%?\\t%0,%1"
   [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
    (set_attr "length" "*,4")
@@ -6017,7 +6016,7 @@ archs4x, archs4xd"
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "q,c")
 		     (const_int 1)))]
   ""
-  "lsr%? %0,%1"
+  "lsr%?\\t%0,%1"
   [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
    (set_attr "predicable" "no,no")])
@@ -6027,7 +6026,7 @@ archs4x, archs4xd"
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "q,c")
 		     (const_int 1)))]
   ""
-  "asr%? %0,%1"
+  "asr%?\\t%0,%1"
   [(set_attr "type" "unary")
    (set_attr "iscompact" "maybe,false")
    (set_attr "predicable" "no,no")])
@@ -6167,7 +6166,7 @@ archs4x, archs4xd"
 		  (sign_extend:DI (match_dup 2)))
 	 (reg:DI ARCV2_ACC)))]
  "TARGET_PLUS_MACD"
- "macd %0,%1,%2"
+ "macd\\t%0,%1,%2"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no,no")
@@ -6210,7 +6209,7 @@ archs4x, archs4xd"
 	  (reg:DI ARCV2_ACC))))
    (clobber (reg:DI ARCV2_ACC))]
  "TARGET_PLUS_DMPY"
- "mac %0,%1,%2"
+ "mac\\t%0,%1,%2"
   [(set_attr "length" "4,8")
    (set_attr "type" "multi")
    (set_attr "predicable" "no")
@@ -6269,7 +6268,7 @@ archs4x, archs4xd"
 		  (zero_extend:DI (match_dup 2)))
 	 (reg:DI ARCV2_ACC)))]
  "TARGET_PLUS_MACD"
- "macdu %0,%1,%2"
+ "macdu\\t%0,%1,%2"
   [(set_attr "length" "4,4,8")
    (set_attr "type" "multi")
    (set_attr "predicable" "yes,no,no")
@@ -6312,7 +6311,7 @@ archs4x, archs4xd"
 	  (reg:DI ARCV2_ACC))))
    (clobber (reg:DI ARCV2_ACC))]
  "TARGET_PLUS_DMPY"
- "macu %0,%1,%2"
+ "macu\\t%0,%1,%2"
   [(set_attr "length" "4,8")
    (set_attr "type" "multi")
    (set_attr "predicable" "no")
