From patchwork Mon Nov 6 18:37:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 162122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp2853160vqu; Mon, 6 Nov 2023 10:37:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IEVMS9CdYBrXaLuQtw7XuTNZTvt8Z6j38TWZLH8X+gwBaIdoIywpvpQqoNSXDQJbyP6b7/P X-Received: by 2002:a25:c541:0:b0:d9a:5ff4:cfde with SMTP id v62-20020a25c541000000b00d9a5ff4cfdemr29917532ybe.13.1699295867364; Mon, 06 Nov 2023 10:37:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699295867; cv=pass; d=google.com; s=arc-20160816; b=mBz+p+NfsZzQFQ/aYUIdG7AiAwqRopmmSJi9ny8sn3U23Mq9xHV7Eofao2SXWgRu6L M/JZgoTSrpcx2opkT2Jg8xS3kqXChBbvHfrrpjtg75joBioaUBiMj0lhHcrGKaT7gcTu TNpnylYGPYksYQm1HBc+Xro3+3OA/39R2yAvZVVyCo17rdKwOA7AoMwLf4fbhvy2Tled BZjQ8EKj425rBiBO+5ADxF8Jw3hMxHmWDsKjSfHNAQGXnPCN5dIcJmpTjvYHsijyTAF6 Rlbx9VA6dIEF7v1lvzEpXknUIA+o+M65nShwjtl40W8L2TppNHk71fszfchjxxOgXqOi h+gg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-language:thread-index :mime-version:message-id:date:subject:cc:to:from:dkim-signature :arc-filter:dmarc-filter:delivered-to; bh=FoBQ28wJ9rlNue7OXLdiOYBRvBrfP4zINjBhubxyZY8=; fh=Ht8bq8SVyF6sx4+E7Os+tBO2MuNVfxRGp/jyiuwYCzE=; b=lFyc7Bggd5EPi0HjhVTQ7NkZlC0dTOzl9PtYY3hO8Rrlf9R4LFCoyp6aKoX9uXlECl WTaarxID1M0r1knYvEMqhAv+mfLZa2mewbaialgWTF3l/ajilOaHWkDqEESh69fxFuEx x01Z72j5PNRt/4DhjNHXQ51gqOoy5Bra8gLIj740qOpvkAkQrdPVWHJstMPMkGQe2BS5 YX2Oh0Rct9bs0MtwoALQM65lNmT3HflnDRze0wRD7Di/ZFmeKvEMJilDa7uEyymAa1wn 9cnKDZQzuH6qwHWZs3EZ2Q1dSjX6CoNQPpVV4q1jA0dEoAPN9h0rH1mt37akMbX7+gb+ vtwA== ARC-Authentication-Results: i=2; mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=rfNn0Kso; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id f7-20020a05620a408700b007776479cb6bsi6044109qko.31.2023.11.06.10.37.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Nov 2023 10:37:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=rfNn0Kso; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1D8AA3857835 for ; Mon, 6 Nov 2023 18:37:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 23F2A3858C66 for ; Mon, 6 Nov 2023 18:37:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 23F2A3858C66 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 23F2A3858C66 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699295844; cv=none; b=OxARDInKbawHm0RI0CdGwtFsCI78bgKnDZxbQFMrR+rR5Xc8liC6qhAt4XdB0fd0A1Utej4FR2kBSZTZ8w5Og6OjZAa0lmcRcihkBz/66rnTjnRBPL5Fw1y4NyEGS0wWBj+z5ndykjVptg2pBw/EtBK9VmNFr9iSeT/HF427lHc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699295844; c=relaxed/simple; bh=JxXUH+bb2DdRfrsFyybeyGNWQHNwfXIHkNFyRXPo3Po=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=i4awfkhAOm397K2ZhSV1+GqJBuiERE8YW7QG8r6oZbLOUl8QSu8OsbeofmF+nZRLZoTsgJWHLJzSFjTjdlLvrnKCgitCSvCkfAxiETgnpAAIDbyToei3xLlRc1zb0rNmzI9SGkZ3oGTwC9BEYUe+sodt27Qr4momC6JIhqumQgk= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=FoBQ28wJ9rlNue7OXLdiOYBRvBrfP4zINjBhubxyZY8=; b=rfNn0Ksozo+hTFl4Xtun3fZCC0 SEbWp0TG1dmCqDfHsvd0QjI90yyh5nLsP7NGJ1UlOzW09IL6PDtQXQmJU7mbGgxFY2j9bkRs+lZhE Bkg8tA0kfQNQUhAdfKv7w/t7lXzf2HsyzN6xHGgeW3R5ZNI2VAlLfNshycPRb6EqCjxQwuP81ERMy bbAEEcWx7QO0f9QueEgAhvz8ynqHr/YOBn6lfODX7mWe9uBonbgReU0G0Jl8hI8/8UibFRXUJu2cj CQ1wnI+1qeZEGXfM7Rzdy9Mhf6NvcYqMWDkOCglKHOPJp2V2Cg09kk38eNkpgf4Z3ml6TDGd29vR+ cLWRxkWg==; Received: from [185.62.158.67] (port=56230 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1r04TP-0006U0-1H; Mon, 06 Nov 2023 13:37:19 -0500 From: "Roger Sayle" To: Cc: "'Claudiu Zissulescu'" Subject: [ARC PATCH] Consistent use of whitespace in assembler templates. Date: Mon, 6 Nov 2023 18:37:15 -0000 Message-ID: <02c901da10e0$4537e260$cfa7a720$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoQ37VleuGJZqHKTwCyFUSVBHhxsg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781840863384210842 X-GMAIL-MSGID: 1781840863384210842 This minor clean-up patch tweaks arc.md to use whitespace consistently in output templates, always using a TAB between the mnemonic and its operands, and avoiding spaces after commas between operands. There should be no functional changes with this patch, though several test cases' scan-assembler needed to be updated to use \s+ instead of testing for a TAB or a space explicitly. Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-11-06 Roger Sayle gcc/ChangeLog * config/arc/arc.md: Make output template whitespace consistent. gcc/testsuite/ChangeLog * gcc.target/arc/jli-1.c: Update dg-final whitespace. * gcc.target/arc/jli-2.c: Likewise. * gcc.target/arc/naked-1.c: Likewise. * gcc.target/arc/naked-2.c: Likewise. * gcc.target/arc/tmac-1.c: Likewise. * gcc.target/arc/tmac-2.c: Likewise. Thanks again, Roger --- diff --git a/gcc/testsuite/gcc.target/arc/jli-1.c b/gcc/testsuite/gcc.target/arc/jli-1.c index f7259b3..2ded750 100644 --- a/gcc/testsuite/gcc.target/arc/jli-1.c +++ b/gcc/testsuite/gcc.target/arc/jli-1.c @@ -14,6 +14,6 @@ int main() return func(100); } -/* { dg-final { scan-assembler "jli_s @__jli.func" } } */ -/* { dg-final { scan-assembler ".weak __jli.func" } } */ +/* { dg-final { scan-assembler "jli_s\\\s+@__jli.func" } } */ +/* { dg-final { scan-assembler ".weak\\\s+__jli.func" } } */ /* { dg-final { scan-assembler "b\\\s+@func" } } */ diff --git a/gcc/testsuite/gcc.target/arc/jli-2.c b/gcc/testsuite/gcc.target/arc/jli-2.c index 96a35a4..347d5b4 100644 --- a/gcc/testsuite/gcc.target/arc/jli-2.c +++ b/gcc/testsuite/gcc.target/arc/jli-2.c @@ -14,6 +14,6 @@ int main() return func(100); } -/* { dg-final { scan-assembler "jli_s 2" } } */ +/* { dg-final { scan-assembler "jli_s\\\s+2" } } */ /* { dg-final { scan-assembler-not ".weak __jli.func" } } */ /* { dg-final { scan-assembler-not "b\\\s+@func" } } */ diff --git a/gcc/testsuite/gcc.target/arc/naked-1.c b/gcc/testsuite/gcc.target/arc/naked-1.c index e45f433f..3705f40 100644 --- a/gcc/testsuite/gcc.target/arc/naked-1.c +++ b/gcc/testsuite/gcc.target/arc/naked-1.c @@ -9,10 +9,10 @@ foo (int n, int m) { bar (n + m); } -/* { dg-final { scan-assembler "\tbl @bar" } } */ +/* { dg-final { scan-assembler "\tbl\\\s+@bar" } } */ /* Look for things that would appear in a non-naked function, but which should not appear in a naked function. */ -/* { dg-final { scan-assembler-not "\tj.* \\\[blink\\\]" } } */ -/* { dg-final { scan-assembler-not "\tst.* " } } */ -/* { dg-final { scan-assembler-not "\tmov fp,sp" } } */ +/* { dg-final { scan-assembler-not "\tj.*\\\s+\\\[blink\\\]" } } */ +/* { dg-final { scan-assembler-not "\tst.*\\\s+" } } */ +/* { dg-final { scan-assembler-not "\tmov\\\s+fp,sp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/naked-2.c b/gcc/testsuite/gcc.target/arc/naked-2.c index 7b7262f..271633e 100644 --- a/gcc/testsuite/gcc.target/arc/naked-2.c +++ b/gcc/testsuite/gcc.target/arc/naked-2.c @@ -16,11 +16,11 @@ foo (int n, int m) { bar (n + m); } -/* { dg-final { scan-assembler "\tbl @bar" } } */ +/* { dg-final { scan-assembler "\tbl\\\s+@bar" } } */ /* Look for things that would appear in a non-naked function, but which should not appear in a naked function. */ /* { dg-final { scan-assembler-not "\trtie" } } */ /* { dg-final { scan-assembler-not "j.*\[ilink1\]" } } */ -/* { dg-final { scan-assembler-not "\tst.* " } } */ -/* { dg-final { scan-assembler-not "\tmov fp,sp" } } */ +/* { dg-final { scan-assembler-not "\tst.*\\\s+" } } */ +/* { dg-final { scan-assembler-not "\tmov\\\s+fp,sp" } } */ diff --git a/gcc/testsuite/gcc.target/arc/tmac-1.c b/gcc/testsuite/gcc.target/arc/tmac-1.c index 5b302ca..797d028 100644 --- a/gcc/testsuite/gcc.target/arc/tmac-1.c +++ b/gcc/testsuite/gcc.target/arc/tmac-1.c @@ -5,7 +5,7 @@ /* Test MAC operation for MPY_OPTION = 8. */ #include "tmac.h" -/* { dg-final { scan-assembler "macd " } } */ +/* { dg-final { scan-assembler "macd\\\s+" } } */ /* { dg-final { scan-assembler "macdu" } } */ -/* { dg-final { scan-assembler "mpyd\\t" } } */ +/* { dg-final { scan-assembler "mpyd\\\s+" } } */ /* { dg-final { scan-assembler "mpydu" } } */ diff --git a/gcc/testsuite/gcc.target/arc/tmac-2.c b/gcc/testsuite/gcc.target/arc/tmac-2.c index 2bd051b..2af7fc1 100644 --- a/gcc/testsuite/gcc.target/arc/tmac-2.c +++ b/gcc/testsuite/gcc.target/arc/tmac-2.c @@ -5,7 +5,7 @@ /* Test MAC operation for MPY_OPTION = 7. */ #include "tmac.h" -/* { dg-final { scan-assembler "mac " } } */ +/* { dg-final { scan-assembler "mac\\\s+" } } */ /* { dg-final { scan-assembler "macu" } } */ -/* { dg-final { scan-assembler "mpym\\t" } } */ +/* { dg-final { scan-assembler "mpym\\\s+" } } */ /* { dg-final { scan-assembler "mpymu" } } */ diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 7702978..846aa32 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -669,26 +669,26 @@ archs4x, archs4xd" || (satisfies_constraint_Cm3 (operands[1]) && memory_operand (operands[0], QImode))" "@ - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - ldb%? %0,%1 - stb%? %1,%0 - ldb%? %0,%1 - xldb%U1 %0,%1 - ldb%U1%V1 %0,%1 - xstb%U0 %1,%0 - stb%U0%V0 %1,%0 - stb%U0%V0 %1,%0 - stb%U0%V0 %1,%0 - stb%U0%V0 %1,%0" + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + ldb%?\\t%0,%1 + stb%?\\t%1,%0 + ldb%?\\t%0,%1 + xldb%U1\\t%0,%1 + ldb%U1%V1\\t%0,%1 + xstb%U0\\t%1,%0 + stb%U0%V0\\t%1,%0 + stb%U0%V0\\t%1,%0 + stb%U0%V0\\t%1,%0 + stb%U0%V0\\t%1,%0" [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,load,store,load,load,load,store,store,store,store,store") (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,false,true,true,true,false,false,false,false,false,false,false") (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,no,no,no,no,no,no,no,no,no,no") @@ -713,26 +713,26 @@ archs4x, archs4xd" || (satisfies_constraint_Cm3 (operands[1]) && memory_operand (operands[0], HImode))" "@ - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 - ld%_%? %0,%1 - st%_%? %1,%0 - xld%_%U1 %0,%1 - ld%_%U1%V1 %0,%1 - xst%_%U0 %1,%0 - st%_%U0%V0 %1,%0 - st%_%U0%V0 %1,%0 - st%_%U0%V0 %1,%0 - st%_%U0%V0 %1,%0" + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 + ld%_%?\\t%0,%1 + st%_%?\\t%1,%0 + xld%_%U1\\t%0,%1 + ld%_%U1%V1\\t%0,%1 + xst%_%U0\\t%1,%0 + st%_%U0%V0\\t%1,%0 + st%_%U0%V0\\t%1,%0 + st%_%U0%V0\\t%1,%0 + st%_%U0%V0\\t%1,%0" [(set_attr "type" "move,move,move,move,move,move,move,move,move,move,move,load,store,load,load,store,store,store,store,store") (set_attr "iscompact" "maybe,maybe,maybe,true,true,false,false,false,maybe_limm,maybe_limm,false,true,true,false,false,false,false,false,false,false") (set_attr "predicable" "yes,no,yes,no,no,yes,no,yes,yes,yes,yes,no,no,no,no,no,no,no,no,no") @@ -818,7 +818,7 @@ archs4x, archs4xd" (plus:SI (reg:SI SP_REG) (match_operand 1 "immediate_operand" "Cal")))))] "reload_completed" - "ld.a %0,[sp,%1]" + "ld.a\\t%0,[sp,%1]" [(set_attr "type" "load") (set_attr "length" "8")]) @@ -830,7 +830,7 @@ archs4x, archs4xd" (unspec:SI [(match_operand:SI 1 "register_operand" "c")] UNSPEC_ARC_DIRECT))] "" - "st%U0 %1,%0\;st%U0.di %1,%0" + "st%U0\\t%1,%0\;st%U0.di\\t%1,%0" [(set_attr "type" "store")]) ;; Combiner patterns for compare with zero @@ -944,7 +944,7 @@ archs4x, archs4xd" (set (match_operand:SI 0 "register_operand" "=w") (match_dup 3))] "" - "%O3.f %0,%1" + "%O3.f\\t%0,%1" [(set_attr "type" "compare") (set_attr "cond" "set_zn") (set_attr "length" "4")]) @@ -987,15 +987,15 @@ archs4x, archs4xd" switch (which_alternative) { case 0: case 2: case 3: case 7: - return \"tst%? %1,%2\"; + return \"tst%?\\t%1,%2\"; case 1: - return \"btst%? %1,%z2\"; + return \"btst%?\\t%1,%z2\"; case 4: - return \"bmsk%?.f 0,%1,%Z2\"; + return \"bmsk%?.f\\t0,%1,%Z2\"; case 5: - return \"bclr%?.f 0,%1,%M2\"; + return \"bclr%?.f\\t0,%1,%M2\"; case 6: - return \"asr.f 0,%1,%p2\"; + return \"asr.f\\t0,%1,%p2\"; default: gcc_unreachable (); } @@ -1026,7 +1026,7 @@ archs4x, archs4xd" && (INTVAL (operands[3]) + INTVAL (operands[2]) <= 11 || (INTVAL (operands[3]) <= 11 && INTVAL (operands[3]) + INTVAL (operands[2]) == 32))" - "tst %1,((1<<%2)-1)<<%3" + "tst\\t%1,((1<<%2)-1)<<%3" [(set_attr "type" "compare") (set_attr "cond" "set_zn") (set_attr "length" "4")]) @@ -1058,11 +1058,11 @@ archs4x, archs4xd" (clobber (match_scratch:SI 4 "=X,X,X,Rrq,X"))] "" "@ - btst%? %1,%3 - btst %1,%3 - bmsk.f 0,%1,%2-1 - movb.f.cl %4,%1,%3,%3,%2 - and.f 0,%1,((1<<%2)-1)<<%3" + btst%?\\t%1,%3 + btst\\t%1,%3 + bmsk.f\\t0,%1,%2-1 + movb.f.cl\\t%4,%1,%3,%3,%2 + and.f\\t0,%1,((1<<%2)-1)<<%3" [(set_attr "iscompact" "maybe,false,false,false,false") (set_attr "type" "compare,compare,compare,shift,compare") (set_attr "cond" "set_zn") @@ -1146,7 +1146,7 @@ archs4x, archs4xd" (set (match_operand:SI 0 "register_operand" "=w,w,w") (match_dup 4))] "" - "%O4.f %0,%1,%2 ; non-mult commutative" + "%O4.f\\t%0,%1,%2 ; non-mult commutative" [(set_attr "type" "compare,compare,compare") (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) @@ -1164,7 +1164,7 @@ archs4x, archs4xd" (set (match_operand:SI 0 "register_operand" "=W,W,W") (match_dup 4))] "!TARGET_ARC600_FAMILY" - "%O4.f %0,%1,%2 ; mult commutative" + "%O4.f\\t%0,%1,%2 ; mult commutative" [(set_attr "type" "compare,compare,compare") (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) @@ -1248,7 +1248,7 @@ archs4x, archs4xd" (set (match_operand:SI 0 "register_operand" "=w,w,w") (and:SI (match_dup 1) (not:SI (match_dup 2))))] "" - "bic.f %0,%1,%2" + "bic.f\\t%0,%1,%2" [(set_attr "type" "compare,compare,compare") (set_attr "cond" "set_zn,set_zn,set_zn") (set_attr "length" "4,4,8")]) @@ -1640,13 +1640,13 @@ archs4x, archs4xd" { if (rtx_equal_p (operands[1], const0_rtx) && GET_CODE (operands[3]) == NE && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)) - return "sub%?.ne %0,%0,%0"; + return "sub%?.ne\\t%0,%0,%0"; /* ??? might be good for speed on ARC600 too, *if* properly scheduled. */ if ((optimize_size && (!TARGET_ARC600_FAMILY)) && rtx_equal_p (operands[1], constm1_rtx) && GET_CODE (operands[3]) == LTU) - return "sbc.cs %0,%0,%0"; - return "mov.%d3 %0,%1"; + return "sbc.cs\\t%0,%0,%0"; + return "mov.%d3\\t%0,%1"; } [(set_attr "type" "cmove,cmove") (set_attr "length" "4,8")]) @@ -1734,11 +1734,11 @@ archs4x, archs4xd" the first register operand 0 is the same as the second register of operand 1, we must copy in the opposite order. */ if (REGNO (operands[0]) == REGNO (operands[1]) + 1) - return \"mov.%d3 %R0,%R1\;mov.%d3 %0,%1\"; + return \"mov.%d3\\t%R0,%R1\;mov.%d3\\t%0,%1\"; else - return \"mov.%d3 %0,%1\;mov.%d3 %R0,%R1\"; + return \"mov.%d3\\t%0,%1\;mov.%d3\\t%R0,%R1\"; case 1 : - return \"mov.%d3 %L0,%L1\;mov.%d3 %H0,%H1\"; + return \"mov.%d3\\t%L0,%L1\;mov.%d3\\t%H0,%H1\"; } @@ -1755,8 +1755,8 @@ archs4x, archs4xd" (match_operand:SF 2 "register_operand" "0,0")))] "" "@ - mov.%d3 %0,%1 - mov.%d3 %0,%1 ; %A1" + mov.%d3\\t%0,%1 + mov.%d3\\t%0,%1 ; %A1" [(set_attr "type" "cmove,cmove")]) (define_insn "*movdfcc_insn" @@ -1776,12 +1776,11 @@ archs4x, archs4xd" the first register operand 0 is the same as the second register of operand 1, we must copy in the opposite order. */ if (REGNO (operands[0]) == REGNO (operands[2]) + 1) - return \"mov.%d1 %R0,%R2\;mov.%d1 %0,%2\"; + return \"mov.%d1\\t%R0,%R2\;mov.%d1\\t%0,%2\"; else - return \"mov.%d1 %0,%2\;mov.%d1 %R0,%R2\"; + return \"mov.%d1\\t%0,%2\;mov.%d1\\t%R0,%R2\"; case 1 : - return \"mov.%d1 %L0,%L2\;mov.%d1 %H0,%H2; %A2 \"; - + return \"mov.%d1\\t%L0,%L2\;mov.%d1\\t%H0,%H2; %A2\"; } }" [(set_attr "type" "cmove,cmove") @@ -1944,7 +1943,7 @@ archs4x, archs4xd" [(set (match_operand:SI 0 "dest_reg_operand" "=q,w,w") (abs:SI (match_operand:SI 1 "nonmemory_operand" "q,cL,Cal")))] "" - "abs%? %0,%1" + "abs%?\\t%0,%1" [(set_attr "type" "two_cycle_core") (set_attr "length" "*,4,8") (set_attr "iscompact" "true,false,false")]) @@ -2031,7 +2030,7 @@ archs4x, archs4xd" (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,r,0, 0, r")) (match_operand:HI 2 "short_const_int_operand" "L,L,I,C16,C16")))] "TARGET_MPYW" - "mpyw%? %0,%1,%2" + "mpyw%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "mul16_em") @@ -2044,7 +2043,7 @@ archs4x, archs4xd" (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0,r")) (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" "q,r,r"))))] "TARGET_MPYW" - "mpyw%? %0,%1,%2" + "mpyw%?\\t%0,%1,%2" [(set_attr "length" "*,4,4") (set_attr "iscompact" "maybe,false,false") (set_attr "type" "mul16_em") @@ -2071,7 +2070,7 @@ archs4x, archs4xd" (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, r, 0, 0, r")) (match_operand:HI 2 "short_unsigned_const_operand" " L, L,J12,J16,J16")))] "TARGET_MPYW" - "mpyuw%? %0,%1,%2" + "mpyuw%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "mul16_em") @@ -2084,7 +2083,7 @@ archs4x, archs4xd" (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, 0, r")) (zero_extend:SI (match_operand:HI 2 "register_operand" "q, r, r"))))] "TARGET_MPYW" - "mpyuw%? %0,%1,%2" + "mpyuw%?\\t%0,%1,%2" [(set_attr "length" "*,4,4") (set_attr "iscompact" "maybe,false,false") (set_attr "type" "mul16_em") @@ -2155,7 +2154,7 @@ archs4x, archs4xd" (const_int 0)))) (clobber (match_operand:SI 3 "acc1_operand" ""))] "TARGET_MULMAC_32BY16_SET" - "mululw 0, %0, %1" + "mululw\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") (set_attr "predicable" "no") @@ -2173,7 +2172,7 @@ archs4x, archs4xd" (match_dup 2))) (clobber (match_operand:SI 3 "acc1_operand" ""))] "TARGET_MULMAC_32BY16_SET" - "machlw%? 0, %0, %1" + "machlw%?\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600, mulmac_600, mulmac_600") (set_attr "predicable" "no, no, yes") @@ -2242,7 +2241,7 @@ archs4x, archs4xd" (sign_extend:DI (match_operand:SI 0 "register_operand" "%q, c,c, c")) (sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "q,cL,L,C32"))))] "TARGET_MUL64_SET" - "mul64%? \t0, %0, %1" + "mul64%?\\t0,%0,%1" [(set_attr "length" "*,4,4,8") (set_attr "iscompact" "maybe,false,false,false") (set_attr "type" "multi,multi,multi,multi") @@ -2277,7 +2276,7 @@ archs4x, archs4xd" (zero_extend:DI (match_operand:SI 0 "register_operand" "%c,c,c")) (zero_extend:DI (match_operand:SI 1 "nonmemory_operand" "cL,L,C32"))))] "TARGET_MUL64_SET" - "mulu64%? \t0, %0, %1" + "mulu64%?\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") (set_attr "type" "umulti") @@ -2401,7 +2400,7 @@ archs4x, archs4xd" (const_int 0)))) ] "TARGET_MULMAC_32BY16_SET" - "mullw%? 0, %0, %1" + "mullw%?\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") (set_attr "predicable" "no,no,yes") @@ -2429,7 +2428,7 @@ archs4x, archs4xd" (reg:DI MUL32x16_REG)) (const_int 32) (const_int 32)))] "TARGET_MULMAC_32BY16_SET" - "machlw%? %0, %1, %2" + "machlw%?\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") (set_attr "predicable" "no,no,yes") @@ -2616,7 +2615,7 @@ archs4x, archs4xd" (const_int 0)))) ] "TARGET_MULMAC_32BY16_SET" - "mululw 0, %0, %1" + "mululw\\t0,%0,%1" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") (set_attr "predicable" "no") @@ -2643,7 +2642,7 @@ archs4x, archs4xd" (reg:DI MUL32x16_REG)) (const_int 32) (const_int 32)))] "TARGET_MULMAC_32BY16_SET" - "machulw%? %0, %1, %2" + "machulw%?\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "mulmac_600") (set_attr "predicable" "no,no,yes") @@ -2824,7 +2823,7 @@ archs4x, archs4xd" ; (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0)) ; (match_operand:SI 1 "register_operand" "c")))] ; "" -; "adc %0,%1,0" +; "adc\\t%0,%1,0" ; [(set_attr "cond" "use") ; (set_attr "type" "cc_arith") ; (set_attr "length" "4")]) @@ -2930,7 +2929,7 @@ archs4x, archs4xd" (ltu:SI (match_operand:CC_C 2 "cc_use_register") (const_int 0))))] "" - "sbc %0,%1,0" + "sbc\\t%0,%1,0" [(set_attr "cond" "use") (set_attr "type" "cc_arith") (set_attr "length" "4")]) @@ -3177,38 +3176,38 @@ archs4x, archs4xd" switch (which_alternative) { case 0: case 5: case 10: case 11: case 16: case 17: case 18: - return "and%? %0,%1,%2"; + return "and%?\\t%0,%1,%2"; case 1: case 6: - return "and%? %0,%2,%1"; + return "and%?\\t%0,%2,%1"; case 2: - return "bmsk%? %0,%1,%Z2"; + return "bmsk%?\\t%0,%1,%Z2"; case 7: case 12: if (satisfies_constraint_C2p (operands[2])) { operands[2] = GEN_INT ((~INTVAL (operands[2]))); - return "bmskn%? %0,%1,%Z2"; + return "bmskn%?\\t%0,%1,%Z2"; } else { - return "bmsk%? %0,%1,%Z2"; + return "bmsk%?\\t%0,%1,%Z2"; } case 3: case 8: case 13: - return "bclr%? %0,%1,%M2"; + return "bclr%?\\t%0,%1,%M2"; case 4: return (INTVAL (operands[2]) == 0xff - ? "extb%? %0,%1" : "ext%_%? %0,%1"); - case 9: case 14: return \"bic%? %0,%1,%n2-1\"; + ? "extb%?\\t%0,%1" : "ext%_%?\\t%0,%1"); + case 9: case 14: return \"bic%?\\t%0,%1,%n2-1\"; case 15: - return "movb.cl %0,%1,%p2,%p2,%x2"; + return "movb.cl\\t%0,%1,%p2,%p2,%x2"; case 19: const char *tmpl; if (satisfies_constraint_Ucm (operands[1])) tmpl = (INTVAL (operands[2]) == 0xff - ? "xldb%U1 %0,%1" : "xld%_%U1 %0,%1"); + ? "xldb%U1\\t%0,%1" : "xld%_%U1\\t%0,%1"); else - tmpl = INTVAL (operands[2]) == 0xff ? "ldb %0,%1" : "ld%_ %0,%1"; + tmpl = INTVAL (operands[2]) == 0xff ? "ldb\\t%0,%1" : "ld%_\\t%0,%1"; if (TARGET_BIG_ENDIAN) { @@ -3254,7 +3253,7 @@ archs4x, archs4xd" (match_operand:SI 2 "nonmemory_operand" "0,0,0,0,r,r,Cal")))] "" "@ - bic%?\\t%0, %2, %1 ;;constraint 0 + bic%?\\t%0,%2,%1 ;;constraint 0 bic%?\\t%0,%2,%1 ;;constraint 1 bic\\t%0,%2,%1 ;;constraint 2, FIXME: will it ever get generated ??? bic%?\\t%0,%2,%1 ;;constraint 3, FIXME: will it ever get generated ??? @@ -3337,7 +3336,7 @@ archs4x, archs4xd" [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") (not:SI (match_operand:SI 1 "register_operand" "q,c")))] "" - "not%? %0,%1" + "not%?\\t%0,%1" [(set_attr "type" "unary,unary") (set_attr "iscompact" "true,false")]) @@ -3599,7 +3598,7 @@ archs4x, archs4xd" (compare:CC (match_operand:SI 0 "register_operand" "q, q, h, c, c, q,c") (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,cL,Cal,Cal")))] "" - "cmp%? %0,%B1" + "cmp%?\\t%0,%B1" [(set_attr "type" "compare") (set_attr "iscompact" "true,true,true,false,false,true_limm,false") (set_attr "predicable" "no,no,no,no,yes,no,yes") @@ -3612,7 +3611,7 @@ archs4x, archs4xd" (compare:CC_ZN (match_operand:SI 0 "register_operand" "q,c") (const_int 0)))] "" - "tst%? %0,%0" + "tst%?\\t%0,%0" [(set_attr "type" "compare,compare") (set_attr "iscompact" "true,false") (set_attr "predicable" "no,yes") @@ -3628,7 +3627,7 @@ archs4x, archs4xd" (match_operand:SI 1 "nonmemory_operand" "L,Lc")) (const_int 0)))] "" - "btst%? %0,%1" + "btst%?\\t%0,%1" [(set_attr "iscompact" "true,false") (set_attr "predicable" "no,yes") (set_attr "cond" "set") @@ -3641,8 +3640,8 @@ archs4x, archs4xd" (match_operand:SI 1 "p2_immediate_operand" "O,n")))] "" "@ - cmp%? %0,%1 - bxor.f 0,%0,%z1" + cmp%?\\t%0,%1 + bxor.f\\t0,%0,%z1" [(set_attr "type" "compare,compare") (set_attr "iscompact" "true,false") (set_attr "cond" "set,set_zn") @@ -3653,7 +3652,7 @@ archs4x, archs4xd" (compare:CC_C (match_operand:SI 0 "register_operand" "q, q, h, c, q, c") (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,Cal,Cal")))] "" - "cmp%? %0,%1" + "cmp%?\\t%0,%1" [(set_attr "type" "compare") (set_attr "iscompact" "true,true,true,false,true_limm,false") (set_attr "cond" "set") @@ -3763,7 +3762,7 @@ archs4x, archs4xd" (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (match_operand:SI 1 "nonmemory_operand" "LRac,?Cal")))] "" - "mov.%d3 %0,%1" + "mov.%d3\\t%0,%1" [(set_attr "type" "cmove") (set_attr "length" "4,8")]) @@ -3799,9 +3798,9 @@ archs4x, archs4xd" (match_operand:SI 2 "nonmemory_operand" "cL,0,0"))))] "" "@ - sub.%d4 %0,%1,%2 - rsub.%d4 %0,%2,%1 - rsub.%d4 %0,%2,%1" + sub.%d4\\t%0,%1,%2 + rsub.%d4\\t%0,%2,%1 + rsub.%d4\\t%0,%2,%1" [(set_attr "cond" "use") (set_attr "type" "cmove") (set_attr "length" "4,4,8")]) @@ -3815,7 +3814,7 @@ archs4x, archs4xd" [(match_operand:SI 1 "register_operand" "0,0") (match_operand:SI 2 "nonmemory_operand" "cL,Cal")])))] "" - "%O3.%d5 %0,%1,%2" + "%O3.%d5\\t%0,%1,%2" [(set_attr "cond" "use") (set_attr "type" "cmove") (set_attr "length" "4,8")]) @@ -3954,11 +3953,11 @@ archs4x, archs4xd" [(set (pc) (match_operand:SI 0 "nonmemory_operand" "L,I,Cal,q,r"))] "" "@ - j%!%* %0 - j%!%* %0 - j%!%* %0 - j%!%* [%0] - j%!%* [%0]" + j%!%*\\t%0 + j%!%*\\t%0 + j%!%*\\t%0 + j%!%*\\t[%0] + j%!%*\\t[%0]" [(set_attr "type" "jump") (set_attr "iscompact" "false,false,false,maybe,false") (set_attr "cond" "canuse,canuse_limm,canuse,canuse,canuse")]) @@ -4122,15 +4121,15 @@ archs4x, archs4xd" (clobber (reg:SI 31))] "" "@ - jl%!%* [%0] - jl%!%* [%0] - jli_s %J0 - sjli %J0 - bl%!%* %P0 - bl%!%* %P0 - jl%!%* %0 - jl%* %0 - jl%! %0" + jl%!%*\\t[%0] + jl%!%*\\t[%0] + jli_s\\t%J0 + sjli\\t%J0 + bl%!%*\\t%P0 + bl%!%*\\t%P0 + jl%!%*\\t%0 + jl%*\\t%0 + jl%!\\t%0" [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") (set_attr "iscompact" "maybe,*,true,*,*,*,*,*,*") (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes") @@ -4166,15 +4165,15 @@ archs4x, archs4xd" (clobber (reg:SI 31))] "" "@ - jl%!%* [%1] - jl%!%* [%1] - jli_s %J1 - sjli %J1 - bl%!%* %P1;1 - bl%!%* %P1;1 - jl%!%* %1 - jl%* %1 - jl%! %1" + jl%!%*\\t[%1] + jl%!%*\\t[%1] + jli_s\\t%J1 + sjli\\t%J1 + bl%!%*\\t%P1;1 + bl%!%*\\t%P1;1 + jl%!%*\\t%1 + jl%*\\t%1 + jl%!\\t%1" [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") (set_attr "iscompact" "maybe,*,true,false,*,*,*,*,*") (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes") @@ -4392,8 +4391,8 @@ archs4x, archs4xd" (clrsb:HI (match_operand:HI 1 "general_operand" "cL,Cal"))))] "TARGET_NORM" "@ - norm%_ \t%0, %1 - norm%_ \t%0, %1" + norm%_\\t%0,%1 + norm%_\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core,two_cycle_core")]) @@ -4496,9 +4495,9 @@ archs4x, archs4xd" UNSPEC_ARC_SWAP))] "TARGET_SWAP" "@ - swap \t%0, %1 - swap \t%0, %1 - swap \t%0, %1" + swap\\t%0,%1 + swap\\t%0,%1 + swap\\t%0,%1" [(set_attr "length" "4,8,4") (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")]) @@ -4509,9 +4508,9 @@ archs4x, archs4xd" UNSPEC_ARC_DIVAW))] "TARGET_ARC700 || TARGET_EA_SET" "@ - divaw \t%0, %1, %2 - divaw \t%0, %1, %2 - divaw \t%0, %1, %2" + divaw\\t%0,%1,%2 + divaw\\t%0,%1,%2 + divaw\\t%0,%1,%2" [(set_attr "length" "4,8,8") (set_attr "type" "divaw,divaw,divaw")]) @@ -4520,9 +4519,9 @@ archs4x, archs4xd" VUNSPEC_ARC_FLAG)] "" "@ - flag%? %0 - flag %0 - flag%? %0" + flag%?\\t%0 + flag\\t%0 + flag%?\\t%0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") (set_attr "predicable" "yes,no,yes") @@ -4572,7 +4571,7 @@ archs4x, archs4xd" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "Lr")] VUNSPEC_ARC_SLEEP)] "" - "sleep %0" + "sleep\\t%0" [(set_attr "length" "4") (set_attr "type" "misc")]) @@ -4596,8 +4595,8 @@ archs4x, archs4xd" "" "* if (check_if_valid_regno_const (operands, 1)) - return \"mov \tr%1, %0\"; - return \"mov \tr%1, %0\"; + return \"mov\\tr%1,%0\"; + return \"mov\\tr%1,%0\"; " [(set_attr "length" "4") (set_attr "type" "unary")]) @@ -4685,7 +4684,7 @@ archs4x, archs4xd" { if (which_alternative == 0) { - return \"trap_s %0\"; + return \"trap_s\\t%0\"; } /* Keep this message in sync with the one in arc.cc:arc_expand_builtin, @@ -4890,7 +4889,7 @@ archs4x, archs4xd" return \"br%d0%*\\t%1,%B2,%l3\"; /* FALLTHRU */ case 6: case 10: - case 12:return \"cmp%? %1, %B2\\n\\tb%d0%*\\t%l3 ;br%d0 out of range\"; + case 12:return \"cmp%?\\t%1,%B2\\n\\tb%d0%*\\t%l3 ;br%d0 out of range\"; default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length (insn)); fflush (stderr); gcc_unreachable (); } " @@ -4952,9 +4951,9 @@ archs4x, archs4xd" switch (get_attr_length (insn)) { case 4: return (GET_CODE (operands[3]) == EQ - ? \"bbit0%* %1,%2,%0\" : \"bbit1%* %1,%2,%0\"); + ? \"bbit0%*\\t%1,%2,%0\" : \"bbit1%*\\t%1,%2,%0\"); case 6: - case 8: return \"btst%? %1,%2\n\tb%d3%* %0; bbit out of range\"; + case 8: return \"btst%?\\t%1,%2\n\tb%d3%*\\t%0; bbit out of range\"; default: gcc_unreachable (); } } @@ -5251,7 +5250,7 @@ archs4x, archs4xd" [(set (match_operand:SI 0 "register_operand" "= r,r") (bswap:SI (match_operand:SI 1 "nonmemory_operand" "rL,Cal")))] "TARGET_V2 && TARGET_SWAP" - "swape %0, %1" + "swape\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "two_cycle_core")]) @@ -5284,9 +5283,9 @@ archs4x, archs4xd" "TARGET_HS" { if (INTVAL (operands[2])) - return "prefetchw [%0, %1]"; + return "prefetchw\\t[%0, %1]"; else - return "prefetch [%0, %1]"; + return "prefetch\\t[%0, %1]"; } [(set_attr "type" "load") (set_attr "length" "4,4,8")]) @@ -5299,9 +5298,9 @@ archs4x, archs4xd" { operands[0] = gen_rtx_MEM (SImode, operands[0]); if (INTVAL (operands[1])) - return "prefetchw%U0 %0"; + return "prefetchw%U0\\t%0"; else - return "prefetch%U0 %0"; + return "prefetch%U0\\t%0"; } [(set_attr "type" "load") (set_attr "length" "8")]) @@ -5311,7 +5310,7 @@ archs4x, archs4xd" (div:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r, r,L,L,I,Cal,Cal")))] "TARGET_DIVREM" - "div%? %0, %1, %2" + "div%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "div_rem") @@ -5324,7 +5323,7 @@ archs4x, archs4xd" (udiv:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r, r,L,L,I,Cal,Cal")))] "TARGET_DIVREM" - "divu%? %0, %1, %2" + "divu%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "div_rem") @@ -5337,7 +5336,7 @@ archs4x, archs4xd" (mod:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r, r,L,L,I,Cal,Cal")))] "TARGET_DIVREM" - "rem%? %0, %1, %2" + "rem%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "div_rem") @@ -5350,7 +5349,7 @@ archs4x, archs4xd" (umod:SI (match_operand:SI 1 "nonmemory_operand" "0,r,Cal,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r, r,L,L,I,Cal,Cal")))] "TARGET_DIVREM" - "remu%? %0, %1, %2" + "remu%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "div_rem") @@ -5366,7 +5365,7 @@ archs4x, archs4xd" (arcCC_cond:SI (match_operand:SI 1 "register_operand" "0,r,0,r,0,0,r") (match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I,n,n")))] "TARGET_V2 && TARGET_CODE_DENSITY" - "set%? %0, %1, %2" + "set%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "compare") @@ -5379,7 +5378,7 @@ archs4x, archs4xd" (ltu:SI (match_operand:SI 1 "register_operand" "0,r,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I, n, n")))] "TARGET_V2 && TARGET_CODE_DENSITY" - "setlo%? %0, %1, %2" + "setlo%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "compare") @@ -5392,7 +5391,7 @@ archs4x, archs4xd" (geu:SI (match_operand:SI 1 "register_operand" "0,r,0,r,0, 0, r") (match_operand:SI 2 "nonmemory_operand" "r,r,L,L,I, n, n")))] "TARGET_V2 && TARGET_CODE_DENSITY" - "seths%? %0, %1, %2" + "seths%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,4,4,8,8") (set_attr "iscompact" "false") (set_attr "type" "compare") @@ -5406,7 +5405,7 @@ archs4x, archs4xd" (gtu:SI (match_operand:SI 1 "register_operand" "r,r, r,r") (match_operand:SI 2 "nonmemory_operand" "0,r,C62,n")))] "TARGET_V2 && TARGET_CODE_DENSITY" - "setlo%? %0, %2, %1" + "setlo%?\\t%0,%2,%1" "reload_completed && CONST_INT_P (operands[2]) && satisfies_constraint_C62 (operands[2])" @@ -5429,7 +5428,7 @@ archs4x, archs4xd" (leu:SI (match_operand:SI 1 "register_operand" "r,r, r,r") (match_operand:SI 2 "nonmemory_operand" "0,r,C62,n")))] "TARGET_V2 && TARGET_CODE_DENSITY" - "seths%? %0, %2, %1" + "seths%?\\t%0,%2,%1" "reload_completed && CONST_INT_P (operands[2]) && satisfies_constraint_C62 (operands[2])" @@ -5492,9 +5491,9 @@ archs4x, archs4xd" VUNSPEC_ARC_KFLAG)] "TARGET_V2" "@ - kflag%? %0 - kflag %0 - kflag%? %0" + kflag%?\\t%0 + kflag\\t%0 + kflag%?\\t%0" [(set_attr "length" "4,4,8") (set_attr "type" "misc,misc,misc") (set_attr "predicable" "yes,no,yes") @@ -5505,7 +5504,7 @@ archs4x, archs4xd" (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "N")] VUNSPEC_ARC_CLRI))] "TARGET_V2" - "clri %0" + "clri\\t%0" [(set_attr "length" "4") (set_attr "type" "misc")]) @@ -5767,7 +5766,7 @@ archs4x, archs4xd" (match_operand:SI 2 "const_int_operand" "n") (match_operand:SI 3 "const_int_operand" "n")))] "TARGET_NPS_BITOPS && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32" - "movb.cl %0,%1,0,%3,%2" + "movb.cl\\t%0,%1,0,%3,%2" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5793,8 +5792,8 @@ archs4x, archs4xd" && (register_operand (operands[3], SImode) || satisfies_constraint_C18 (operands[1]))" "@ - movbi %0,%0,%3,%2,%1 - movb %0,%0,%3,%2,0,%1" + movbi\\t%0,%0,%3,%2,%1 + movb\\t%0,%0,%3,%2,0,%1" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5806,7 +5805,7 @@ archs4x, archs4xd" (match_dup 1) (match_operand:SI 4 "const_int_operand" "n")))] "TARGET_NPS_BITOPS" - "movb %0,%0,%3,%2,%4,%1" + "movb\\t%0,%0,%3,%2,%4,%1" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5818,7 +5817,7 @@ archs4x, archs4xd" (match_dup 1) (match_operand:SI 4 "const_int_operand" "n")))] "TARGET_NPS_BITOPS" - "movb %0,%0,%3,%2,%4,%1" + "movb\\t%0,%0,%3,%2,%4,%1" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5830,7 +5829,7 @@ archs4x, archs4xd" (match_operand:SI 4 "const_int_operand" "n")))] "TARGET_NPS_BITOPS && INTVAL (operands[4]) + INTVAL (operands[1]) <= 32" - "movb %0,%0,%3,%2,%4,%1" + "movb\\t%0,%0,%3,%2,%4,%1" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5845,7 +5844,7 @@ archs4x, archs4xd" (match_operand:SI 4 "const_int_operand" "n")))] "TARGET_NPS_BITOPS && INTVAL (operands[4]) + INTVAL (operands[1]) <= 32" - "movb %0,%0,%3,%2,%4,%1" + "movb\\t%0,%0,%3,%2,%4,%1" [(set_attr "type" "shift") (set_attr "length" "4")]) @@ -5876,7 +5875,7 @@ archs4x, archs4xd" (match_operand:SI 7 "const_int_operand" "n")))] "TARGET_NPS_BITOPS" { - output_asm_insn ("mrgb %0,%0,%6,%2,%3,%1,%5,%7,%4", operands); + output_asm_insn ("mrgb\\t%0,%0,%6,%2,%3,%1,%5,%7,%4", operands); /* The ;%? updates the known unalignment. */ return arc_short_long (insn, ";%?", "nop_s"); } @@ -5995,7 +5994,7 @@ archs4x, archs4xd" (ashift:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" - "asl%? %0,%1" + "asl%?\\t%0,%1" [(set_attr "type" "unary") (set_attr "iscompact" "maybe,false") (set_attr "length" "*,4") @@ -6017,7 +6016,7 @@ archs4x, archs4xd" (lshiftrt:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" - "lsr%? %0,%1" + "lsr%?\\t%0,%1" [(set_attr "type" "unary") (set_attr "iscompact" "maybe,false") (set_attr "predicable" "no,no")]) @@ -6027,7 +6026,7 @@ archs4x, archs4xd" (ashiftrt:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" - "asr%? %0,%1" + "asr%?\\t%0,%1" [(set_attr "type" "unary") (set_attr "iscompact" "maybe,false") (set_attr "predicable" "no,no")]) @@ -6167,7 +6166,7 @@ archs4x, archs4xd" (sign_extend:DI (match_dup 2))) (reg:DI ARCV2_ACC)))] "TARGET_PLUS_MACD" - "macd %0,%1,%2" + "macd\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,no") @@ -6210,7 +6209,7 @@ archs4x, archs4xd" (reg:DI ARCV2_ACC)))) (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" - "mac %0,%1,%2" + "mac\\t%0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "multi") (set_attr "predicable" "no") @@ -6269,7 +6268,7 @@ archs4x, archs4xd" (zero_extend:DI (match_dup 2))) (reg:DI ARCV2_ACC)))] "TARGET_PLUS_MACD" - "macdu %0,%1,%2" + "macdu\\t%0,%1,%2" [(set_attr "length" "4,4,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,no") @@ -6312,7 +6311,7 @@ archs4x, archs4xd" (reg:DI ARCV2_ACC)))) (clobber (reg:DI ARCV2_ACC))] "TARGET_PLUS_DMPY" - "macu %0,%1,%2" + "macu\\t%0,%1,%2" [(set_attr "length" "4,8") (set_attr "type" "multi") (set_attr "predicable" "no")