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Date: Thu, 2 Nov 2023 11:50:38 -0000 Message-ID: <025901da0d82$cd5aa3f0$680febd0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoNgkElUwMGwhOpQSuNYzaEwUGDtg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781452898865853016 X-GMAIL-MSGID: 1781452898865853016 This patch optimizes a few special cases in avr.md's *insv.any_shift. instruction. This template handles tests for a single bit, where the result has only a (different) single bit set in the result. Usually (currently) this always requires a three-instruction sequence of a BST, a CLR and a BLD (plus any additional CLR instructions to clear the rest of the result bytes). The special cases considered here are those that can be done with only two instructions (plus CLRs); an ANDI preceded by either a MOV, a SHIFT or a SWAP. Hence for C=1 in HImode, GCC with -O2 currently generates: bst r24,1 clr r24 clr r25 bld r24,0 with this patch, we now generate: lsr r24 andi r24,1 clr r25 Likewise, HImode C=4 now becomes: swap r24 andi r24,1 clr r25 and SImode C=8 now becomes: mov r22,r23 andi r22,1 clr 23 clr 24 clr 25 I've not attempted to model the instruction length accurately for these special cases; the logic would be ugly, but it's safe to use the current (1 insn longer) length. This patch has been (partially) tested with a cross-compiler to avr-elf hosted on x86_64, without a simulator, where the compile-only tests in the gcc testsuite show no regressions. If someone could test this more thoroughly that would be great. 2023-11-02 Roger Sayle gcc/ChangeLog * config/avr/avr.md (*insv.any_shift.): Optimize special cases of *insv.any_shift that save one instruction by using ANDI with either a MOV, a SHIFT or a SWAP. gcc/testsuite/ChangeLog * gcc.target/avr/insvhi-1.c: New HImode test case. * gcc.target/avr/insvhi-2.c: Likewise. * gcc.target/avr/insvhi-3.c: Likewise. * gcc.target/avr/insvhi-4.c: Likewise. * gcc.target/avr/insvhi-5.c: Likewise. * gcc.target/avr/insvqi-1.c: New QImode test case. * gcc.target/avr/insvqi-2.c: Likewise. * gcc.target/avr/insvqi-3.c: Likewise. * gcc.target/avr/insvqi-4.c: Likewise. * gcc.target/avr/insvsi-1.c: New SImode test case. * gcc.target/avr/insvsi-2.c: Likewise. * gcc.target/avr/insvsi-3.c: Likewise. * gcc.target/avr/insvsi-4.c: Likewise. * gcc.target/avr/insvsi-5.c: Likewise. * gcc.target/avr/insvsi-6.c: Likewise. Thanks in advance, Roger diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 83dd15040b07..c2a1931733f8 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -9840,6 +9840,7 @@ (clobber (reg:CC REG_CC))] "reload_completed" { + int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]); int shift = == ASHIFT ? INTVAL (operands[2]) : -INTVAL (operands[2]); int mask = GET_MODE_MASK (mode) & INTVAL (operands[3]); // Position of the output / input bit, respectively. @@ -9850,6 +9851,217 @@ operands[3] = GEN_INT (obit); operands[2] = GEN_INT (ibit); + /* Special cases requiring MOV to low byte and ANDI. */ + if ((shift & 7) == 0 && ldi_ok) + { + if (IN_RANGE (obit, 0, 7)) + { + if (shift == -8) + { + if ( == 2) + return "mov %A0,%B1\;andi %A0,lo8(1<<%3)\;clr %B0"; + if ( == 3) + return "mov %A0,%B1\;andi %A0,lo8(1<<%3)\;clr %B0\;clr %C0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %A0,%B1\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + else if (shift == -16) + { + if ( == 3) + return "mov %A0,%C1\;andi %A0,lo8(1<<%3)\;clr %B0\;clr %C0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %A0,%C1\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + else if (shift == -24 && !AVR_HAVE_MOVW) + return "mov %A0,%D1\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + + /* Special cases requiring MOV and ANDI. */ + else if (IN_RANGE (obit, 8, 15)) + { + if (shift == 8) + { + if ( == 2) + return "mov %B0,%A1\;andi %B0,lo8(1<<(%3-8))\;clr %A0"; + if ( == 3) + return "mov %B0,%A1\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %B0,%A1\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + else if (shift == -8) + { + if ( == 3) + return "mov %B0,%C1\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %B0,%C1\;andi %B0,lo8(1<<(%3-8))\;" + "clr %B0\;clr %C0\;clr %D0"; + } + else if (shift == -16 && !AVR_HAVE_MOVW) + return "mov %B0,%D1\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + else if (IN_RANGE (obit, 16, 23)) + { + if (shift == 16) + { + if ( == 3) + return "mov %C0,%A1\;andi %B0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %C0,%A1\;andi %B0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0\;clr %D0"; + } + else if (shift == 8) + { + if ( == 3) + return "mov %C0,%B1\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0"; + if ( == 4 && !AVR_HAVE_MOVW) + return "mov %C0,%B1\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + else if (shift == -8 && !AVR_HAVE_MOVW) + return "mov %C0,%D1\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0\;clr %D0"; + } + else if (IN_RANGE (obit, 24, 31) && !AVR_HAVE_MOVW) + { + if (shift == 8) + return "mov %D0,%C1\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + if (shift == 16) + return "mov %D0,%B1\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + if (shift == 24) + return "mov %D0,%A1\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + } + } + + /* Special cases where the byte is already in place. */ + if (REGNO (operands[0]) == REGNO (operands[1]) + && ldi_ok) + { + if (shift == 1) + { + if (IN_RANGE (obit, 0, 7)) + { + if ( == 1) + return "lsl %0\;andi %0,lo8(1<<%3)"; + if ( == 2) + return "lsl %A0\;andi %A0,lo8(1<<%3)\;clr %B0"; + if ( == 3) + return "lsl %A0\;andi %A0,lo8(1<<%3)\;clr %B0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "lsl %A0\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + else if (IN_RANGE (obit, 9, 15)) + { + if ( == 2) + return "lsl %B0\;andi %B0,lo8(1<<(%3-8))\;clr %A0"; + if ( == 3) + return "lsl %B0\;andi %B0,lo8(1<<(%3-8))\;clr %A0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "lsl %B0\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + else if (IN_RANGE (obit, 17, 23)) + { + if ( == 3) + return "lsl %C0\;andi %C0,lo8(1<<(%3-16))\;clr %A0\;clr %B0"; + if (!AVR_HAVE_MOVW) + return "lsl %C0\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0\;clr %D0"; + } + else if (IN_RANGE (obit, 25, 31) && !AVR_HAVE_MOVW) + return "lsl %D0\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + } + + if (shift == -1) + { + if (IN_RANGE (obit, 0, 6)) + { + if ( == 1) + return "lsr %0\;andi %0,lo8(1<<%3)"; + if ( == 2) + return "lsr %A0\;andi %A0,lo8(1<<%3)\;clr %B0"; + if ( == 3) + return "lsr %A0\;andi %A0,lo8(1<<%3)\;clr %B0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "lsr %A0\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + else if (IN_RANGE (obit, 8, 14)) + { + if ( == 2) + return "lsr %B0\;andi %B0,lo8(1<<(%3-8))\;clr %A0"; + if ( == 3) + return "lsr %B0\;andi %A0,lo8(1<<(%3-8))\;clr %A0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "lsr %B0\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + else if (IN_RANGE (obit, 16, 22)) + { + if ( == 3) + return "lsr %C0\;andi %C0,lo8(1<<(%3-16))\;clr %A0\;clr %B0"; + if (!AVR_HAVE_MOVW) + return "lsr %C0\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0\;clr %D0"; + } + else if (IN_RANGE (obit, 24, 30) && !AVR_HAVE_MOVW) + return "lsr %D0\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + } + + if ((shift == 4 && IN_RANGE (obit, 4, 7)) + || (shift == -4 && IN_RANGE (obit, 0, 3))) + { + if ( == 1) + return "swap %0\;andi %0,lo8(1<<%3)"; + if ( == 2) + return "swap %A0\;andi %A0,lo8(1<<%3)\;clr %B0"; + if ( == 3) + return "swap %A0\;andi %A0,lo8(1<<%3)\;clr %B0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "swap %A0\;andi %A0,lo8(1<<%3)\;" + "clr %B0\;clr %C0\;clr %D0"; + } + if ((shift == 4 && IN_RANGE (obit, 12, 15)) + || (shift == -4 && IN_RANGE (obit, 8, 11))) + { + if ( == 2) + return "swap %B0\;andi %B0,lo8(1<<(%3-8))\;clr %A0"; + if ( == 3) + return "swap %B0\;andi %B0,lo8(1<<(%3-8))\;clr %A0\;clr %C0"; + if (!AVR_HAVE_MOVW) + return "swap %B0\;andi %B0,lo8(1<<(%3-8))\;" + "clr %A0\;clr %C0\;clr %D0"; + } + if ((shift == 4 && IN_RANGE (obit, 20, 23)) + || (shift == -4 && IN_RANGE (obit, 16, 19))) + { + if ( == 3) + return "swap %C0\;andi %C0,lo8(1<<(%3-16))\;clr %A0\;clr %B0"; + if (!AVR_HAVE_MOVW) + return "swap %C0\;andi %C0,lo8(1<<(%3-16))\;" + "clr %A0\;clr %B0\;clr %D0"; + } + if (((shift == 4 && IN_RANGE (obit, 28, 31)) + || (shift == -4 && IN_RANGE (obit, 24, 27))) + && !AVR_HAVE_MOVW) + return "swap %D0\;andi %D0,lo8(1<<(%3-24))\;" + "clr %A0\;clr %B0\;clr %C0"; + } + if ( == 1) return "bst %T1%T2\;clr %0\;" "bld %T0%T3"; if ( == 2) return "bst %T1%T2\;clr %A0\;clr %B0\;" "bld %T0%T3"; if ( == 3) return "bst %T1%T2\;clr %A0\;clr %B0\;clr %C0\;bld %T0%T3"; diff --git a/gcc/testsuite/gcc.target/avr/insvhi-1.c b/gcc/testsuite/gcc.target/avr/insvhi-1.c new file mode 100644 index 000000000000..4468917b7696 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvhi-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short foo(unsigned short x) +{ + return x & 1; +} + +/* { dg-final { scan-assembler "andi r24,1" } } */ +/* { dg-final { scan-assembler "clr r25" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvhi-2.c b/gcc/testsuite/gcc.target/avr/insvhi-2.c new file mode 100644 index 000000000000..6899fbd0b994 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvhi-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short foo(unsigned short x) +{ + return (x >> 1) & 1; +} + +/* { dg-final { scan-assembler "lsr r24" } } */ +/* { dg-final { scan-assembler "andi r24,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler "clr r25" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvhi-3.c b/gcc/testsuite/gcc.target/avr/insvhi-3.c new file mode 100644 index 000000000000..2d1d9f413dc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvhi-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short foo(unsigned short x) +{ + return (x >> 2) & 1; +} + +/* { dg-final { scan-assembler "bst r24,2" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 2 } } */ +/* { dg-final { scan-assembler "bld r24,0" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvhi-4.c b/gcc/testsuite/gcc.target/avr/insvhi-4.c new file mode 100644 index 000000000000..6a36f4ca6112 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvhi-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short foo(unsigned short x) +{ + return (x >> 4) & 1; +} + +/* { dg-final { scan-assembler "swap r24" } } */ +/* { dg-final { scan-assembler "andi r24,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler "clr r25" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvhi-5.c b/gcc/testsuite/gcc.target/avr/insvhi-5.c new file mode 100644 index 000000000000..6a6e8684a2b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvhi-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned short foo(unsigned short x) +{ + return (x >> 8) & 1; +} + +/* { dg-final { scan-assembler "mov r24,r25" } } */ +/* { dg-final { scan-assembler "andi r24,1" } } */ +/* { dg-final { scan-assembler "ldi r25,0" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvqi-1.c b/gcc/testsuite/gcc.target/avr/insvqi-1.c new file mode 100644 index 000000000000..32f53f226d81 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvqi-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo(unsigned char x) +{ + return x & 1; +} + +/* { dg-final { scan-assembler "andi r24,lo8\\(1\\)" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvqi-2.c b/gcc/testsuite/gcc.target/avr/insvqi-2.c new file mode 100644 index 000000000000..b276b2b3b92f --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvqi-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo(unsigned char x) +{ + return (x>>1) & 1; +} + +/* { dg-final { scan-assembler "lsr r24" } } */ +/* { dg-final { scan-assembler "andi r24,1" } } */ + diff --git a/gcc/testsuite/gcc.target/avr/insvqi-3.c b/gcc/testsuite/gcc.target/avr/insvqi-3.c new file mode 100644 index 000000000000..c28320f64c81 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvqi-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo(unsigned char x) +{ + return (x>>2) & 1; +} + +/* { dg-final { scan-assembler "bst r24,2" } } */ +/* { dg-final { scan-assembler "clr r24" } } */ +/* { dg-final { scan-assembler "bld r24,0" } } */ + diff --git a/gcc/testsuite/gcc.target/avr/insvqi-4.c b/gcc/testsuite/gcc.target/avr/insvqi-4.c new file mode 100644 index 000000000000..1ae7afe92a5b --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvqi-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned char foo(unsigned char x) +{ + return (x>>4) & 1; +} + +/* { dg-final { scan-assembler "swap r24" } } */ +/* { dg-final { scan-assembler "andi r24,1" } } */ + diff --git a/gcc/testsuite/gcc.target/avr/insvsi-1.c b/gcc/testsuite/gcc.target/avr/insvsi-1.c new file mode 100644 index 000000000000..e057a7a09183 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return x & 1; +} + +/* { dg-final { scan-assembler "andi r22,1" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 3 } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvsi-2.c b/gcc/testsuite/gcc.target/avr/insvsi-2.c new file mode 100644 index 000000000000..518340322ce3 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return (x >> 1) & 1; +} + +/* { dg-final { scan-assembler "lsr r22" } } */ +/* { dg-final { scan-assembler "andi r22,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 3 } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvsi-3.c b/gcc/testsuite/gcc.target/avr/insvsi-3.c new file mode 100644 index 000000000000..c8d6e1a8ea23 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return (x >> 2) & 1; +} + +/* { dg-final { scan-assembler "bst r22,2" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 4 } } */ +/* { dg-final { scan-assembler "bld r22,0" } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvsi-4.c b/gcc/testsuite/gcc.target/avr/insvsi-4.c new file mode 100644 index 000000000000..52a3a75203e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-4.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return (x >> 4) & 1; +} + +/* { dg-final { scan-assembler "swap r22" } } */ +/* { dg-final { scan-assembler "andi r22,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 3 } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvsi-5.c b/gcc/testsuite/gcc.target/avr/insvsi-5.c new file mode 100644 index 000000000000..627016a5ae66 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return (x >> 8) & 1; +} + +/* { dg-final { scan-assembler "mov r22,r23" } } */ +/* { dg-final { scan-assembler "andi r22,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 3 } } */ diff --git a/gcc/testsuite/gcc.target/avr/insvsi-6.c b/gcc/testsuite/gcc.target/avr/insvsi-6.c new file mode 100644 index 000000000000..6f72d6a74232 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/insvsi-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +unsigned long foo(unsigned long x) +{ + return (x >> 16) & 1; +} + +/* { dg-final { scan-assembler "mov r22,r24" } } */ +/* { dg-final { scan-assembler "andi r22,lo8\\(1<<0\\)" } } */ +/* { dg-final { scan-assembler-times "clr r2\\d" 3 } } */