diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2a60df5..22f18c2 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9710,33 +9710,29 @@
   [(parallel [(set (match_operand:<DWI> 0 "register_operand")
 		   (mult:<DWI>
 		     (any_extend:<DWI>
-		       (match_operand:DWIH 1 "nonimmediate_operand"))
+		       (match_operand:DWIH 1 "register_operand"))
 		     (any_extend:<DWI>
-		       (match_operand:DWIH 2 "register_operand"))))
+		       (match_operand:DWIH 2 "nonimmediate_operand"))))
 	      (clobber (reg:CC FLAGS_REG))])])
 
 (define_expand "<u>mulqihi3"
   [(parallel [(set (match_operand:HI 0 "register_operand")
 		   (mult:HI
 		     (any_extend:HI
-		       (match_operand:QI 1 "nonimmediate_operand"))
+		       (match_operand:QI 1 "register_operand"))
 		     (any_extend:HI
-		       (match_operand:QI 2 "register_operand"))))
+		       (match_operand:QI 2 "nonimmediate_operand"))))
 	      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_QIMODE_MATH")
 
 (define_insn "*bmi2_umul<mode><dwi>3_1"
   [(set (match_operand:DWIH 0 "register_operand" "=r")
 	(mult:DWIH
-	  (match_operand:DWIH 2 "nonimmediate_operand" "%d")
+	  (match_operand:DWIH 2 "register_operand" "%d")
 	  (match_operand:DWIH 3 "nonimmediate_operand" "rm")))
    (set (match_operand:DWIH 1 "register_operand" "=r")
-	(truncate:DWIH
-	  (lshiftrt:<DWI>
-	    (mult:<DWI> (zero_extend:<DWI> (match_dup 2))
-			(zero_extend:<DWI> (match_dup 3)))
-	    (match_operand:QI 4 "const_int_operand"))))]
-  "TARGET_BMI2 && INTVAL (operands[4]) == <MODE_SIZE> * BITS_PER_UNIT
+	(umul_highpart:DWIH (match_dup 2) (match_dup 3)))]
+  "TARGET_BMI2
    && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "mulx\t{%3, %0, %1|%1, %0, %3}"
   [(set_attr "type" "imulx")
@@ -9747,7 +9743,7 @@
   [(set (match_operand:<DWI> 0 "register_operand" "=r,A")
 	(mult:<DWI>
 	  (zero_extend:<DWI>
-	    (match_operand:DWIH 1 "nonimmediate_operand" "%d,0"))
+	    (match_operand:DWIH 1 "register_operand" "%d,a"))
 	  (zero_extend:<DWI>
 	    (match_operand:DWIH 2 "nonimmediate_operand" "rm,rm"))))
    (clobber (reg:CC FLAGS_REG))]
@@ -9783,11 +9779,7 @@
   [(parallel [(set (match_dup 3)
 		   (mult:DWIH (match_dup 1) (match_dup 2)))
 	      (set (match_dup 4)
-		   (truncate:DWIH
-		     (lshiftrt:<DWI>
-		       (mult:<DWI> (zero_extend:<DWI> (match_dup 1))
-				   (zero_extend:<DWI> (match_dup 2)))
-		       (match_dup 5))))])]
+		   (umul_highpart:DWIH (match_dup 1) (match_dup 2)))])]
 {
   split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);
 
@@ -9798,7 +9790,7 @@
   [(set (match_operand:<DWI> 0 "register_operand" "=A")
 	(mult:<DWI>
 	  (sign_extend:<DWI>
-	    (match_operand:DWIH 1 "nonimmediate_operand" "%0"))
+	    (match_operand:DWIH 1 "register_operand" "%a"))
 	  (sign_extend:<DWI>
 	    (match_operand:DWIH 2 "nonimmediate_operand" "rm"))))
    (clobber (reg:CC FLAGS_REG))]
@@ -9818,7 +9810,7 @@
   [(set (match_operand:HI 0 "register_operand" "=a")
 	(mult:HI
 	  (any_extend:HI
-	    (match_operand:QI 1 "nonimmediate_operand" "%0"))
+	    (match_operand:QI 1 "register_operand" "%0"))
 	  (any_extend:HI
 	    (match_operand:QI 2 "nonimmediate_operand" "qm"))))
    (clobber (reg:CC FLAGS_REG))]
@@ -9835,6 +9827,51 @@
    (set_attr "bdver1_decode" "direct")
    (set_attr "mode" "QI")])
 
+;; Widening multiplication peephole2s to tweak register allocation.
+;; mov imm,%rdx; mov %rdi,%rax; mulq %rdx  ->  mov imm,%rax; mulq %rdi
+(define_peephole2
+  [(set (match_operand:DWIH 0 "general_reg_operand")
+	(match_operand:DWIH 1 "immediate_operand"))
+   (set (match_operand:DWIH 2 "general_reg_operand")
+	(match_operand:DWIH 3 "general_reg_operand"))
+   (parallel [(set (match_operand:<DWI> 4 "general_reg_operand")
+		   (mult:<DWI> (zero_extend:<DWI> (match_dup 2))
+			       (zero_extend:<DWI> (match_dup 0))))
+	      (clobber (reg:CC FLAGS_REG))])]
+  "REGNO (operands[3]) != AX_REG
+   && REGNO (operands[0]) != REGNO (operands[2])
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && (REGNO (operands[0]) == REGNO (operands[4])
+       || REGNO (operands[0]) == DX_REG
+       || peep2_reg_dead_p (3, operands[0]))"
+  [(set (match_dup 2) (match_dup 1))
+   (parallel [(set (match_dup 4)
+		   (mult:<DWI> (zero_extend:<DWI> (match_dup 2))
+			       (zero_extend:<DWI> (match_dup 3))))
+	      (clobber (reg:CC FLAGS_REG))])])
+
+;; mov imm,%rax; mov %rdi,%rdx; mulx %rax  ->  mov imm,%rdx; mulx %rdi
+(define_peephole2
+  [(set (match_operand:DWIH 0 "general_reg_operand")
+	(match_operand:DWIH 1 "immediate_operand"))
+   (set (match_operand:DWIH 2 "general_reg_operand")
+	(match_operand:DWIH 3 "general_reg_operand"))
+   (parallel [(set (match_operand:DWIH 4 "general_reg_operand")
+		   (mult:DWIH (match_dup 2) (match_dup 0)))
+	      (set (match_operand:DWIH 5 "general_reg_operand")
+		   (umul_highpart:DWIH (match_dup 2) (match_dup 0)))])]
+  "REGNO (operands[3]) != DX_REG
+   && REGNO (operands[0]) != REGNO (operands[2])
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && (REGNO (operands[0]) == REGNO (operands[4])
+       || REGNO (operands[0]) == REGNO (operands[5])
+       || peep2_reg_dead_p (3, operands[0]))"
+  [(set (match_dup 2) (match_dup 1))
+   (parallel [(set (match_dup 4)
+		   (mult:DWIH (match_dup 2) (match_dup 3)))
+	      (set (match_dup 5)
+		   (umul_highpart:DWIH (match_dup 2) (match_dup 3)))])])
+
 ;; Highpart multiplication patterns
 (define_insn "<s>mul<mode>3_highpart"
   [(set (match_operand:DWIH 0 "register_operand" "=d")
diff --git a/gcc/testsuite/gcc.target/i386/pr110511.c b/gcc/testsuite/gcc.target/i386/pr110511.c
new file mode 100644
index 0000000..142b808
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110511.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+typedef unsigned long long uint64_t;
+
+uint64_t mulx64(uint64_t x)
+{
+    __uint128_t r = (__uint128_t)x * 0x9E3779B97F4A7C15ull;
+    return (uint64_t)r ^ (uint64_t)( r >> 64 );
+}
+
+/* { dg-final { scan-assembler-not "movq" } } */
