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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v20-20020a170906565400b00993320628absi326025ejr.675.2023.08.03.12.15.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 12:15:25 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=m1Zunek8; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CF545385770C for ; Thu, 3 Aug 2023 19:15:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 493043858D35 for ; Thu, 3 Aug 2023 19:14:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 493043858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=EbCJIbRhf69gZPkGVTsmIrysESheBnW9GXCxXIR5R4w=; b=m1Zunek88qxopnhiqKEmole5AX WVaHcAjZGMVWbqjitkmhEBzN2GLLAF5rTTZzZYdhcqJ3zay/MfQBk77/YJTY2NNtxFuhxiMjbSsGF 7KH9/obVHx5uNF6ilEIvw3/mh69Alozvl+W/XVGYwjer3j0ABSov/ySBIOeK9DRXKdLPNmHgcn/XF tZIU7dffgKv0hHeQUccwzbBOVMCF5IIBF2EE27WHHnwam/PqEl/VHxR+MCnPVuPy2DvK2YUbUnKpu mUtvKI7Vl/XMyVHy8ScOSgEzY8LprMZSLuXiNqut/JiJ/BjTXX5kkZm45TuzpBuC937d7VtPi9yYI 33nupwxg==; Received: from host86-161-68-50.range86-161.btcentralplus.com ([86.161.68.50]:50234 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qRdmX-0001s8-0F for gcc-patches@gcc.gnu.org; Thu, 03 Aug 2023 15:14:45 -0400 From: "Roger Sayle" To: Subject: [PATCH] Specify signed/unsigned/dontcare in calls to extract_bit_field_1. Date: Thu, 3 Aug 2023 20:14:43 +0100 Message-ID: <014d01d9c63e$c36294b0$4a27be10$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Content-Language: en-gb Thread-Index: AdnGPfODx6eOctLlQzeGhneh777YEg== X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773236519829980139 X-GMAIL-MSGID: 1773236519829980139 This patch is inspired by Jakub's work on PR rtl-optimization/110717. The bitfield example described in comment #2, looks like: struct S { __int128 a : 69; }; unsigned type bar (struct S *p) { return p->a; } which on x86_64 with -O2 currently generates: bar: movzbl 8(%rdi), %ecx movq (%rdi), %rax andl $31, %ecx movq %rcx, %rdx salq $59, %rdx sarq $59, %rdx ret The ANDL $31 is interesting... we first extract an unsigned 69-bit bitfield by masking/clearing the top bits of the most significant word, and then it gets sign-extended, by left shifting and arithmetic right shifting. Obviously, this bit-wise AND is redundant, for signed bit-fields, we don't require these bits to be cleared, if we're about to set them appropriately. This patch eliminates this redundancy in the middle-end, during RTL expansion, but extending the extract_bit_field APIs so that the integer UNSIGNEDP argument takes a special value; 0 indicates the field should be sign extended, 1 (any non-zero value) indicates the field should be zero extended, but -1 indicates a third option, that we don't care how or whether the field is extended. By passing and checking this sentinel value at the appropriate places we avoid the useless bit masking (on all targets). For the test case above, with this patch we now generate: bar: movzbl 8(%rdi), %ecx movq (%rdi), %rax movq %rcx, %rdx salq $59, %rdx sarq $59, %rdx ret This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32} with no new failures. Ok for mainline? 2023-08-03 Roger Sayle gcc/ChangeLog * expmed.cc (extract_bit_field_1): Document that an UNSIGNEDP value of -1 is equivalent to don't care. (extract_integral_bit_field): Indicate that we don't require the most significant word to be zero extended, if we're about to sign extend it. (extract_fixed_bit_field_1): Document that an UNSIGNEDP value of -1 is equivalent to don't care. Don't clear the most most significant bits with AND mask when UNSIGNEDP is -1. gcc/testsuite/ChangeLog * gcc.target/i386/pr110717-2.c: New test case. Thanks in advance, Roger diff --git a/gcc/expmed.cc b/gcc/expmed.cc index fbd4ce2..b294eabb 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1631,6 +1631,7 @@ extract_bit_field_as_subreg (machine_mode mode, rtx op0, } /* A subroutine of extract_bit_field, with the same arguments. + If UNSIGNEDP is -1, the result need not be sign or zero extended. If FALLBACK_P is true, fall back to extract_fixed_bit_field if we can find no other means of implementing the operation. if FALLBACK_P is false, return NULL instead. */ @@ -1933,7 +1934,8 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, rtx result_part = extract_bit_field_1 (op0, MIN (BITS_PER_WORD, bitsize - i * BITS_PER_WORD), - bitnum + bit_offset, 1, target_part, + bitnum + bit_offset, + (unsignedp ? 1 : -1), target_part, mode, word_mode, reverse, fallback_p, NULL); gcc_assert (target_part); @@ -2187,6 +2189,7 @@ extract_fixed_bit_field (machine_mode tmode, rtx op0, /* Helper function for extract_fixed_bit_field, extracts the bit field always using MODE, which is the mode of OP0. + If UNSIGNEDP is -1, the result need not be sign or zero extended. The other arguments are as for extract_fixed_bit_field. */ static rtx @@ -2231,7 +2234,8 @@ extract_fixed_bit_field_1 (machine_mode tmode, rtx op0, scalar_int_mode mode, /* Unless the msb of the field used to be the msb when we shifted, mask out the upper bits. */ - if (GET_MODE_BITSIZE (mode) != bitnum + bitsize) + if (GET_MODE_BITSIZE (mode) != bitnum + bitsize + && unsignedp != -1) return expand_binop (new_mode, and_optab, op0, mask_rtx (new_mode, 0, bitsize, 0), target, 1, OPTAB_LIB_WIDEN); diff --git a/gcc/testsuite/gcc.target/i386/pr110717-2.c b/gcc/testsuite/gcc.target/i386/pr110717-2.c new file mode 100644 index 0000000..a3cb568 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110717-2.c @@ -0,0 +1,20 @@ +/* PR target/110717 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#ifdef __SIZEOF_INT128__ +#define type __int128 +#define N 59 +#else +#define type long long +#define N 27 +#endif + +struct S { type a : sizeof (type) * __CHAR_BIT__ - N; }; + +unsigned type bar (struct S *p) +{ + return p->a; +} + +/* { dg-final { scan-assembler-not "andl" } } */