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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j123-20020a1feb81000000b0048f8fbb3a57si472690vkh.274.2023.10.28.06.06.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 06:06:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=qrYnhrql; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 692B7386185F for ; Sat, 28 Oct 2023 13:06:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id DC4153858414 for ; Sat, 28 Oct 2023 13:05:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC4153858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DC4153858414 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698498350; cv=none; b=Dkl7FCgObj+akSVIWOdtEYr98Ww1aOcYNQh+2itpBF/kGoE1avGjyZTjUirpSitanBA0Q3dylet1mfOaPyN2cliTx+cOdP1LCErDQOp1dPR47S1xSjkOh+APOYP1nzKX42N01ieUbGFSq7SaqRmT2iK1xLHJ9kf4XXs7nL7bqpI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698498350; c=relaxed/simple; bh=yp2c+gb8FrozRjrcOwzFuLG+IkFj5/B6XQj3Sk5jde4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=sAB+DfVBGolVdi/Tt4vVp/c9lDy83VN+3UkpHcoxZ/N7hgpl+hyfWT2NtTwoYVZT9qBxYgxhheXeCAiCfwkaBOuOZYC23WlkptUxvoCjnDldn5W0xg0Us+mqfGAB6B7q/Xhdpwx17bUkjvIAMa46TsSm52UxaSAI5fsTmTJ+AHE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=5VFpKM1KOJdyW3ymm5K+kGb5uUN150h6CXW15lhal0o=; b=qrYnhrqlBLnPEfDaAS1w8x6q/P 1bz3PqIckB7oD1EI4vBTsfeJwm8yExapYJZ/Cf/PneW3COGd6OFGxM4KfmMLooEjlWhg0fJQiGrE/ ih/HH4iJmpuEsfGthykJfuOmGPrcA08HHU+zZ2yRw7jLVDejNl3ceTLWMqxx4Dq3vGv/Su6megZL9 GHRFEOXpRWljUERKmGalVQ9yvDRbgnYjmAz27pMFcbR8oCLWx28DV+LjD3R8D9dkU1q6ZXQLqvNT5 QM+cODBs/tOVYrU+HBBm69bP7pk2oNo+TnfWqcj7DTfp/Rtr16ffVAP4CbARH4rfXKCcTI1QLlu2a cnv80KNQ==; Received: from host86-160-20-38.range86-160.btcentralplus.com ([86.160.20.38]:54734 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1qwj0c-0001rO-0X; Sat, 28 Oct 2023 09:05:47 -0400 From: "Roger Sayle" To: Cc: "'Claudiu Zissulescu'" Subject: [ARC PATCH] Improve DImode left shift by a single bit. Date: Sat, 28 Oct 2023 14:05:43 +0100 Message-ID: <010701da099f$76c4a5e0$644df1a0$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoJnpROSOEwikH4QLW3JdBNCS9HCw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781004632127143215 X-GMAIL-MSGID: 1781004632127143215 This patch improves the code generated for X << 1 (and for X + X) when X is 64-bit DImode, using the same two instruction code sequence used for DImode addition. For the test case: long long foo(long long x) { return x << 1; } GCC -O2 currently generates the following code: foo: lsr r2,r0,31 asl_s r1,r1,1 asl_s r0,r0,1 j_s.d [blink] or_s r1,r1,r2 and on CPU without a barrel shifter, i.e. -mcpu=em foo: add.f 0,r0,r0 asl_s r1,r1 rlc r2,0 asl_s r0,r0 j_s.d [blink] or_s r1,r1,r2 with this patch (both with and without a barrel shifter): foo: add.f r0,r0,r0 j_s.d [blink] adc r1,r1,r1 [For Jeff Law's benefit a similar optimization is also applicable to H8300H, that could also use a two instruction sequence (plus rts) but currently GCC generates 16 instructions (plus an rts) for foo above.] Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-10-28 Roger Sayle gcc/ChangeLog * config/arc/arc.md (addsi3): Fix GNU-style code formatting. (adddi3): Change define_expand to generate an *adddi3. (*adddi3): New define_insn_and_split to lower DImode additions during the split1 pass (after combine and before reload). (ashldi3): New define_expand to (only) generate *ashldi3_cnt1 for DImode left shifts by a single bit. (*ashldi3_cnt1): New define_insn_and_split to lower DImode left shifts by one bit to an *adddi3. gcc/testsuite/ChangeLog * gcc.target/arc/adddi3-1.c: New test case. * gcc.target/arc/ashldi3-1.c: Likewise. Thanks in advance, Roger diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ee43887..fe5f48c 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2675,19 +2675,28 @@ archs4x, archs4xd" (plus:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" - "if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[2], false)) - { - operands[2]=force_reg(SImode, operands[2]); - } - ") +{ + if (flag_pic && arc_raw_symbolic_reference_mentioned_p (operands[2], false)) + operands[2] = force_reg (SImode, operands[2]); +}) (define_expand "adddi3" + [(parallel + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "nonmemory_operand" ""))) + (clobber (reg:CC CC_REG))])]) + +(define_insn_and_split "*adddi3" [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "nonmemory_operand" ""))) (clobber (reg:CC CC_REG))] - "" - " + "arc_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ rtx l0 = gen_lowpart (SImode, operands[0]); rtx h0 = gen_highpart (SImode, operands[0]); rtx l1 = gen_lowpart (SImode, operands[1]); @@ -2719,11 +2728,12 @@ archs4x, archs4xd" gen_rtx_LTU (VOIDmode, gen_rtx_REG (CC_Cmode, CC_REG), GEN_INT (0)), gen_rtx_SET (h0, plus_constant (SImode, h0, 1)))); DONE; - } + } emit_insn (gen_add_f (l0, l1, l2)); emit_insn (gen_adc (h0, h1, h2)); DONE; -") +} + [(set_attr "length" "8")]) (define_insn "add_f" [(set (reg:CC_C CC_REG) @@ -3461,6 +3471,33 @@ archs4x, archs4xd" [(set_attr "type" "shift") (set_attr "length" "16,20")]) +;; DImode shifts + +(define_expand "ashldi3" + [(parallel + [(set (match_operand:DI 0 "register_operand") + (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand:QI 2 "const_int_operand"))) + (clobber (reg:CC CC_REG))])] + "" +{ + if (operands[2] != const1_rtx) + FAIL; +}) + +(define_insn_and_split "*ashldi3_cnt1" + [(set (match_operand:DI 0 "register_operand") + (ashift:DI (match_operand:DI 1 "register_operand") + (const_int 1))) + (clobber (reg:CC CC_REG))] + "arc_pre_reload_split ()" + "#" + "&& 1" + [(parallel [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 1))) + (clobber (reg:CC CC_REG))])] + "" + [(set_attr "length" "8")]) + ;; Rotate instructions. (define_insn "rotrsi3_insn" diff --git a/gcc/testsuite/gcc.target/arc/adddi3-1.c b/gcc/testsuite/gcc.target/arc/adddi3-1.c new file mode 100644 index 0000000..b3077c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/adddi3-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long long foo(long long x, long long y) +{ + return x + y; +} + +/* { dg-final { scan-assembler "add.f\\s+r0,r0,r2" } } */ +/* { dg-final { scan-assembler "adc\\s+r1,r1,r3" } } */ diff --git a/gcc/testsuite/gcc.target/arc/ashldi3-1.c b/gcc/testsuite/gcc.target/arc/ashldi3-1.c new file mode 100644 index 0000000..6fe4ff4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/ashldi3-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long long foo(long long x) +{ + return x << 1; +} + +/* { dg-final { scan-assembler "add.f\\s+r0,r0,r0" } } */ +/* { dg-final { scan-assembler "adc\\s+r1,r1,r1" } } */