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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hv16-20020a17090760d000b0083b6e04f379si26196676ejc.492.2023.01.02.02.51.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 02:51:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=bfrMTsoq; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 374E33858425 for ; Mon, 2 Jan 2023 10:51:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 56BA53858D32 for ; Mon, 2 Jan 2023 10:50:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=4PMQ05jxaLIlZByEJ+tEJ4GBTqdn1FWzYSHcVscOqJo=; b=bfrMTsoqhb/Cu6+5nPP/pOxdw3 F3bPohp3yBgApl3uo1HHVq5CnfKUY+LfzE9sLn7FCknVhIB5XKUVLCLTyr9Jc9Ox+yMnKlb1YKCcY CAuHKsY6du9JLN2I4QDBCf5kRMS0UrxrNgRXgSvspMSsWc2kQs1d37xqGxqETSV978sCcEFCG2QZz iPcIm6CU7qXY2vKdbWSWtxAKuRCl0wMZGhYP43KFekzkIbO7YVpMWHd/PElYL6VbwhKQaop6hAXZh QlhrCAm6Mex7PFT2reLXICMnEiDF8w/jOf0IHm3YZy1Bap85zytWFqLwosq7YaIUj6XrCfJagaT0M pV3xvAYA==; Received: from host86-163-35-31.range86-163.btcentralplus.com ([86.163.35.31]:59674 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pCIOv-0001Qx-VH; Mon, 02 Jan 2023 05:50:42 -0500 From: "Roger Sayle" To: "'GCC Patches'" Cc: "'Uros Bizjak'" Subject: [x86 PATCH] Improve ix86_expand_int_movcc to allow condition (mask) sharing. Date: Mon, 2 Jan 2023 10:50:38 -0000 Message-ID: <00c101d91e98$0fc74480$2f55cd80$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdkelqPxDaCfWvucQ4asPcbxUI6GWg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753907649370225746?= X-GMAIL-MSGID: =?utf-8?q?1753907649370225746?= This patch modifies the way that ix86_expand_int_movcc generates RTL, to allow the condition mask to be shared/reused between multiple conditional move sequences. Such redundancy is common when RTL if-conversion transforms non-trivial basic blocks. As a motivating example, consider the new test case: int a, b, c, d; int foo(int x) { if (x == 0) { a = 3; b = 1; c = 4; d = 1; } else { a = 5; b = 9; c = 2; d = 7; } return x; } This is currently compiled, with -O2, to: foo: cmpl $1, %edi movl %edi, %eax sbbl %edi, %edi andl $-2, %edi addl $5, %edi cmpl $1, %eax sbbl %esi, %esi movl %edi, a(%rip) andl $-8, %esi addl $9, %esi cmpl $1, %eax sbbl %ecx, %ecx movl %esi, b(%rip) andl $2, %ecx addl $2, %ecx cmpl $1, %eax sbbl %edx, %edx movl %ecx, c(%rip) andl $-6, %edx addl $7, %edx movl %edx, d(%rip) ret Notice that the if-then-else blocks have been if-converted into four conditional move sequences/assignments, each consisting of cmpl, sbbl, andl and addl. However, as the conditions are the same, the cmpl and sbbl instructions used to generate the mask could be shared by CSE. This patch enables that, so we now generate: foo: cmpl $1, %edi movl %edi, %eax sbbl %edx, %edx movl %edx, %edi movl %edx, %esi movl %edx, %ecx andl $-6, %edx andl $-2, %edi andl $-8, %esi andl $2, %ecx addl $7, %edx addl $5, %edi addl $9, %esi addl $2, %ecx movl %edx, d(%rip) movl %edi, a(%rip) movl %esi, b(%rip) movl %ecx, c(%rip) ret Notice, the code now contains only a single cmpl and a single sbbl, with their result being shared (via movl). This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2023-01-02 Roger Sayle gcc/ChangeLog * config/i386/i386-expand.cc (ix86_expand_int_movcc): Rewrite RTL expansion to allow condition (mask) to be shared/reused, by avoiding overwriting pseudos and adding REG_EQUAL notes. gcc/testsuite/ChangeLog * gcc.target/i386/cmov10.c: New test case. Thanks in advance, Roger diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 3eddbc9..4fd7c3c 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -3284,8 +3284,8 @@ ix86_expand_int_movcc (rtx operands[]) || negate_cc_compare_p || ix86_expand_carry_flag_compare (code, op0, op1, &compare_op)) { - /* Detect overlap between destination and compare sources. */ - rtx tmp = out; + /* Place comparison result in its own pseudo. */ + rtx tmp = gen_reg_rtx (mode); if (negate_cc_compare_p) { @@ -3295,7 +3295,6 @@ ix86_expand_int_movcc (rtx operands[]) emit_insn (gen_x86_negsi_ccc (gen_reg_rtx (SImode), gen_lowpart (SImode, op0))); - tmp = gen_reg_rtx (mode); if (mode == DImode) emit_insn (gen_x86_movdicc_0_m1_neg (tmp)); else @@ -3337,9 +3336,6 @@ ix86_expand_int_movcc (rtx operands[]) } diff = ct - cf; - if (reg_overlap_mentioned_p (out, compare_op)) - tmp = gen_reg_rtx (mode); - if (mode == DImode) emit_insn (gen_x86_movdicc_0_m1 (tmp, flags, compare_op)); else @@ -3358,6 +3354,11 @@ ix86_expand_int_movcc (rtx operands[]) tmp = emit_store_flag (tmp, code, op0, op1, VOIDmode, 0, -1); } + /* Add a REG_EQUAL note to allow condition to be shared. */ + rtx note = gen_rtx_fmt_ee (code, mode, op0, op1); + set_unique_reg_note (get_last_insn (), REG_EQUAL, + gen_rtx_NEG (mode, note)); + if (diff == 1) { /* @@ -3368,9 +3369,8 @@ ix86_expand_int_movcc (rtx operands[]) * Size 5 - 8. */ if (ct) - tmp = expand_simple_binop (mode, PLUS, - tmp, GEN_INT (ct), - copy_rtx (tmp), 1, OPTAB_DIRECT); + tmp = expand_simple_binop (mode, PLUS, tmp, GEN_INT (ct), + NULL_RTX, 1, OPTAB_DIRECT); } else if (cf == -1) { @@ -3381,9 +3381,8 @@ ix86_expand_int_movcc (rtx operands[]) * * Size 8. */ - tmp = expand_simple_binop (mode, IOR, - tmp, GEN_INT (ct), - copy_rtx (tmp), 1, OPTAB_DIRECT); + tmp = expand_simple_binop (mode, IOR, tmp, GEN_INT (ct), + NULL_RTX, 1, OPTAB_DIRECT); } else if (diff == -1 && ct) { @@ -3395,11 +3394,10 @@ ix86_expand_int_movcc (rtx operands[]) * * Size 8 - 11. */ - tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1); + tmp = expand_simple_unop (mode, NOT, tmp, NULL_RTX, 1); if (cf) - tmp = expand_simple_binop (mode, PLUS, - copy_rtx (tmp), GEN_INT (cf), - copy_rtx (tmp), 1, OPTAB_DIRECT); + tmp = expand_simple_binop (mode, PLUS, tmp, GEN_INT (cf), + NULL_RTX, 1, OPTAB_DIRECT); } else { @@ -3417,22 +3415,18 @@ ix86_expand_int_movcc (rtx operands[]) { cf = ct; ct = 0; - tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1); + tmp = expand_simple_unop (mode, NOT, tmp, NULL_RTX, 1); } - tmp = expand_simple_binop (mode, AND, - copy_rtx (tmp), + tmp = expand_simple_binop (mode, AND, tmp, gen_int_mode (cf - ct, mode), - copy_rtx (tmp), 1, OPTAB_DIRECT); + NULL_RTX, 1, OPTAB_DIRECT); if (ct) - tmp = expand_simple_binop (mode, PLUS, - copy_rtx (tmp), GEN_INT (ct), - copy_rtx (tmp), 1, OPTAB_DIRECT); + tmp = expand_simple_binop (mode, PLUS, tmp, GEN_INT (ct), + NULL_RTX, 1, OPTAB_DIRECT); } - if (!rtx_equal_p (tmp, out)) - emit_move_insn (copy_rtx (out), copy_rtx (tmp)); - + emit_move_insn (out, tmp); return true; } diff --git a/gcc/testsuite/gcc.target/i386/cmov10.c b/gcc/testsuite/gcc.target/i386/cmov10.c new file mode 100644 index 0000000..142b4d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cmov10.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +int a, b, c, d; + +int foo(int x) +{ + if (x == 0) { + a = 3; + b = 1; + c = 4; + d = 1; + } else { + a = 5; + b = 9; + c = 2; + d = 7; + } + return x; +} +/* { dg-final { scan-assembler-times "cmpl" 1 } } */ +/* { dg-final { scan-assembler-times "sbbl" 1 } } */