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[8.43.85.97]) by mx.google.com with ESMTPS id h19-20020a05640250d300b0046bc9cbd8f0si1807409edb.504.2022.12.22.15.10.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 15:10:11 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b=mi1QknPk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E78873850F1C for ; Thu, 22 Dec 2022 23:10:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 20CDD3858D1E for ; Thu, 22 Dec 2022 23:09:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 20CDD3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=zI1hpF/UGbwsvQsHXI7in5gtWsmV95olbJcxxJq+9FY=; b=mi1QknPknTc/72Q37eReEdEMqA hAzoFGThd9z7ElxMY9/GF3HflKRveZB+wvq+JReDxIixGUBbDqEOT4GaWo1yNcv1B64kxKqDmsdsM m3hUYS8Jf0GsuO6fAK/8TVw+8qHbZjArrxXh4pE03lOGuz0MgEOcMseWRvMJG0Ydtg2zgN1Wv1pQn K8YWSnpjUbhdvmc0udUMMASZKCplbS8ROCGug9o3OWa5f0HKoHu17ydNh97RYWelCl1/KJHqmjvGH 2oZE3P+dAYRX43EtqjAsuFWLDlUTVrfpUttt6FsCUYPq5bOuwo9/ZZ2QJogD0V4VjzVSEQksS7xXT z4Np6seQ==; Received: from host109-151-228-216.range109-151.btcentralplus.com ([109.151.228.216]:60470 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p8Ugu-0001FP-TJ; Thu, 22 Dec 2022 18:09:33 -0500 From: "Roger Sayle" To: "'GCC Patches'" Cc: "'Uros Bizjak'" , "'H.J. Lu'" Subject: [x86 PATCH] PR target/106933: Limit TImode STV to SSA-like def-use chains. Date: Thu, 22 Dec 2022 23:09:31 -0000 Message-ID: <001001d9165a$73e9cc30$5bbd6490$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdkWWMK5OT1gRU6wQw+QOxjERFk9Cw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752957569399306732?= X-GMAIL-MSGID: =?utf-8?q?1752957569399306732?= With many thanks to H.J. for doing all the hard work, this patch resolves two P1 regressions; PR target/106933 and PR target/106959. Although superficially similar, the i386 backend's two scalar-to-vector (STV) passes perform their transformations in importantly different ways. The original pass converting SImode and DImode operations to V4SImode or V2DImode operations is "soft", allowing values to be maintained in both integer and vector hard registers. The newer pass converting TImode operations to V1TImode is "hard" (all or nothing) that converts all uses of a pseudo to vector form. To implement this it invokes powerful ju-ju calling SET_MODE on a REG_rtx, which due to RTL sharing, often updates this pseudo's mode everywhere in the RTL chain. Hence, TImode STV can only be performed when all uses of a pseudo are convertible to V1TImode form. To ensure this the STV passes currently use data-flow analysis to inspect all DEFs and USEs in a chain. This works fine for chains that are in the usual single assignment form, but the occurrence of uninitialized variables, or multiple assignments that split a pseudo's usage into several independent chains (lifetimes) can lead to situations where some but not all of a pseudo's occurrences need to be updated. This is safe for the SImode/DImode pass, but leads to the above bugs during the TImode pass. My one minor tweak to HJ's patch from comment #4 of bugzilla PR106959 is to only perform the new single_def_chain_p check for TImode STV; it turns out that STV of SImode/DImode min/max operates safely on multiple-def chains, and prohibiting this leads to testsuite regressions. We don't (yet) support V1TImode min/max, so this idiom isn't an issue during the TImode STV pass. For the record, the two alternate possible fixes are (i) make the TImode STV pass "soft", by eliminating use of SET_MODE, instead using replace_rtx with a new pseudo, or (ii) merging "chains" so that multiple DFA chains/lifetimes are considered a single STV chain. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-12-22 H.J. Lu Roger Sayle gcc/ChangeLog PR target/106933 PR target/106959 * config/i386/i386-features.cc (single_def_chain_p): New predicate function to check that a pseudo's use-def chain is in SSA form. (timode_scalar_to_vector_candidate_p): Check that TImode regs that are SET_DEST or SET_SRC of an insn match/are single_def_chain_p. gcc/testsuite/ChangeLog PR target/106933 PR target/106959 * gcc.target/i386/pr106933-1.c: New test case. * gcc.target/i386/pr106933-2.c: Likewise. * gcc.target/i386/pr106959-1.c: Likewise. * gcc.target/i386/pr106959-2.c: Likewise. * gcc.target/i386/pr106959-3.c: Likewise. Thanks in advance, Roger diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index fd212262..4bf8bb3 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -1756,6 +1756,19 @@ pseudo_reg_set (rtx_insn *insn) return set; } +/* Return true if the register REG is defined in a single DEF chain. + If it is defined in more than one DEF chains, we may not be able + to convert it in all chains. */ + +static bool +single_def_chain_p (rtx reg) +{ + df_ref ref = DF_REG_DEF_CHAIN (REGNO (reg)); + if (!ref) + return false; + return DF_REF_NEXT_REG (ref) == nullptr; +} + /* Check if comparison INSN may be transformed into vector comparison. Currently we transform equality/inequality checks which look like: (set (reg:CCZ 17 flags) (compare:CCZ (reg:TI x) (reg:TI y))) */ @@ -1972,9 +1985,14 @@ timode_scalar_to_vector_candidate_p (rtx_insn *insn) && !TARGET_SSE_UNALIGNED_STORE_OPTIMAL) return false; + if (REG_P (dst) && !single_def_chain_p (dst)) + return false; + switch (GET_CODE (src)) { case REG: + return single_def_chain_p (src); + case CONST_WIDE_INT: return true; diff --git a/gcc/testsuite/gcc.target/i386/pr106933-1.c b/gcc/testsuite/gcc.target/i386/pr106933-1.c new file mode 100644 index 0000000..bcd9576 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106933-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +short int +bar (void); + +__int128 +empty (void) +{ +} + +__attribute__ ((simd)) int +foo (__int128 *p) +{ + int a = 0x80000000; + + *p = empty (); + + return *p == (a < bar ()); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr106933-2.c b/gcc/testsuite/gcc.target/i386/pr106933-2.c new file mode 100644 index 0000000..ac7d07e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106933-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-msse4 -Os" } */ + +__int128 n; + +__int128 +empty (void) +{ +} + +int +foo (void) +{ + n = empty (); + + return n == 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr106959-1.c b/gcc/testsuite/gcc.target/i386/pr106959-1.c new file mode 100644 index 0000000..4bac2a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106959-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-msse4 -O2 -fno-tree-loop-im --param max-combine-insns=2 -Wno-shift-count-overflow" } */ + +unsigned __int128 n; + +int +foo (int x) +{ + __int128 a = 0; + int b = !!(n * 2); + + while (x < 2) + { + if (a) + { + if (n) + n ^= 1; + else + x <<= 32; + } + + a = 1; + } + + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/pr106959-2.c b/gcc/testsuite/gcc.target/i386/pr106959-2.c new file mode 100644 index 0000000..29f0c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106959-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-msse4 -O2 -fno-tree-loop-im -Wno-shift-count-overflow" } */ + +unsigned __int128 n; + +int +foo (int x) +{ + __int128 a = 0; + int b = !!(n * 2); + + while (x < 2) + { + if (a) + { + if (n) + n ^= 1; + else + x <<= 32; + } + + a = 1; + } + + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/pr106959-3.c b/gcc/testsuite/gcc.target/i386/pr106959-3.c new file mode 100644 index 0000000..0f58f13 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr106959-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -fpeel-loops" } */ + +unsigned __int128 m; +int n; + +__attribute__ ((simd)) void +foo (int x) +{ + x = n ? n : (short int) x; + if (x) + m /= 2; +} +