Show patches with: Submitter = Jiawei       |    Archived = No       |   23 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add XiangShan Nanhu microarchitecture. RISC-V: Add XiangShan Nanhu microarchitecture. - - - -1- 2024-02-27 Jiawei Unresolved
[v2] RISC-V: Supports RISC-V Profiles in '-march' option. [v2] RISC-V: Supports RISC-V Profiles in '-march' option. - - - -1- 2023-12-12 Jiawei Unresolved
[RFC] RISC-V: Support RISC-V Profiles in -march option. [RFC] RISC-V: Support RISC-V Profiles in -march option. - - - -1- 2023-11-20 Jiawei Unresolved
[v2,3/3] RISC-V: Add ZC* test for failed march args being passed. RISC-V: Support ZC* extensions. - - - 1-- 2023-06-07 Jiawei Accepted
[v2,2/3] RISC-V: Enable compressible features when use ZC* extensions. RISC-V: Support ZC* extensions. - - - 1-- 2023-06-07 Jiawei Accepted
[v2,1/3] RISC-V: Minimal support for ZC* extensions. RISC-V: Support ZC* extensions. - - - 1-- 2023-06-07 Jiawei Accepted
[5/5] RISC-V: Add ZCMP push/pop testcases. RISC-V: Support ZC* extensions. - - - 1-- 2023-04-06 Jiawei Accepted
[4/5] RISC-V: Add Zcmp extension supports. RISC-V: Support ZC* extensions. - - - 1-- 2023-04-06 Jiawei Accepted
[3/5] RISC-V: Add ZC* test for march args being passed. RISC-V: Support ZC* extensions. - - - 1-- 2023-04-06 Jiawei Accepted
[2/5] RISC-V: Enable compressible features when use ZC* extensions. RISC-V: Support ZC* extensions. - - - 1-- 2023-04-06 Jiawei Accepted
[1/5] RISC-V: Minimal support for ZC extensions. RISC-V: Support ZC* extensions. - - - 1-- 2023-04-06 Jiawei Accepted
[v3] RISC-V: Add Z*inx imcompatible check in gcc [v3] RISC-V: Add Z*inx imcompatible check in gcc - - - 1-- 2023-03-28 Jiawei Accepted
[v2] RISC-V: Add Z*inx imcompatible check in gcc. [v2] RISC-V: Add Z*inx imcompatible check in gcc. - - - 1-- 2023-03-28 Jiawei Accepted
RISC-V: Add Z*inx incompatible check in gcc. RISC-V: Add Z*inx incompatible check in gcc. - - - 1-- 2023-03-26 Jiawei Accepted
[v2,2/2] RISC-V: Optimize RVV epilogue logic. RISC-V: Optimize RVV epilogue logic. - - - 1-- 2022-11-15 Jiawei Accepted
[v2,1/2] RISC-V: Add spill sp adjust check testcase. RISC-V: Optimize RVV epilogue logic. - - - 1-- 2022-11-15 Jiawei Accepted
RISC-V: Optimal RVV epilogue logic. RISC-V: Optimal RVV epilogue logic. - - - 1-- 2022-11-14 Jiawei Accepted
[RFC] RISC-V: Add profile supports. [RFC] RISC-V: Add profile supports. - - - 1-- 2022-11-02 Jiawei Accepted
[RFC] RISC-V: Minimal supports for new extensions in profile. [RFC] RISC-V: Minimal supports for new extensions in profile. - - - 1-- 2022-11-02 Jiawei Accepted
[v4,4/4] RISC-V: Add zhinx/zhinxmin testcases. RISC-V: Support z*inx extensions. - - - 1-- 2022-10-20 Jiawei Accepted
[v4,3/4] RISC-V: Limit regs use for z*inx extension. RISC-V: Support z*inx extensions. - - - 1-- 2022-10-20 Jiawei Accepted
[v4,2/4] RISC-V: Target support for z*inx extension. RISC-V: Support z*inx extensions. - - - 1-- 2022-10-20 Jiawei Accepted
[v4,1/4] RISC-V: Minimal support of z*inx extension. RISC-V: Support z*inx extensions. - - - 1-- 2022-10-20 Jiawei Accepted