Show patches with: Submitter = Jivan Hakobyan       |    Archived = No       |   15 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add type attribute in *<optab>_not_const<mode> pattern RISC-V: Add type attribute in *<optab>_not_const<mode> pattern - - - -1- 2023-09-29 Jivan Hakobyan Unresolved
[V2] RISC-V: Replace not + bitwise_imm with li + bitwise_not [V2] RISC-V: Replace not + bitwise_imm with li + bitwise_not - - - 1-- 2023-09-12 Jivan Hakobyan Accepted
RISC-V: Replace not + bitwise_imm with li + bitwise_not RISC-V: Replace not + bitwise_imm with li + bitwise_not - - - 1-- 2023-09-11 Jivan Hakobyan Accepted
RISC-V: Fix stack_save_restore_1/2 test cases RISC-V: Fix stack_save_restore_1/2 test cases - - - -1- 2023-08-24 Jivan Hakobyan Unresolved
RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn RISC-V: Replace unspec with bitreverse in riscv_brev8_<mode> insn - - - 1-- 2023-07-26 Jivan Hakobyan Accepted
RISC-V: Folding memory for FP + constant case RISC-V: Folding memory for FP + constant case - - - 1-- 2023-07-12 Jivan Hakobyan Accepted
LTO: buffer overflow in lto_output_init_mode_table LTO: buffer overflow in lto_output_init_mode_table - - - 1-- 2023-06-22 Jivan Hakobyan Accepted
[wwwdocs] Broken URL to README in st/cli-be project [wwwdocs] Broken URL to README in st/cli-be project - - - -1- 2023-06-14 Jivan Hakobyan Unresolved
Remove MFWRAP_SPEC remnant Remove MFWRAP_SPEC remnant - - - 1-- 2023-06-14 Jivan Hakobyan Accepted
[RFC] RISC-V: Eliminate extension after for *w instructions [RFC] RISC-V: Eliminate extension after for *w instructions - - - -1- 2023-05-24 Jivan Hakobyan Unresolved
RISC-V: Use extension instructions instead of bitwise "and" RISC-V: Use extension instructions instead of bitwise "and" - - - 1-- 2023-05-23 Jivan Hakobyan Accepted
[v2] RISC-V: Remove masking third operand of rotate instructions [v2] RISC-V: Remove masking third operand of rotate instructions - - - 1-- 2023-05-17 Jivan Hakobyan Accepted
RISC-V: Remove masking third operand of rotate instructions RISC-V: Remove masking third operand of rotate instructions - - - 1-- 2023-05-10 Jivan Hakobyan Accepted
RISC-V: Eliminate redundant zero extension of minu/maxu operands RISC-V: Eliminate redundant zero extension of minu/maxu operands - - - 1-- 2023-04-28 Jivan Hakobyan Accepted
RISC-V: avoid splitting small constants in bcrli_nottwobits patterns RISC-V: avoid splitting small constants in bcrli_nottwobits patterns - - - 1-- 2023-04-20 Jivan Hakobyan Accepted