Show patches with: Submitter = Raphael Moreira Zinsly       |    Archived = No       |   8 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add Veyron V1 pipeline description RISC-V: Add Veyron V1 pipeline description - - - 1-- 2023-06-07 Raphael Moreira Zinsly Accepted
[v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] [v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] - - - 1-- 2023-05-08 Raphael Moreira Zinsly Accepted
[v2] RISC-V: Add bext pattern for ZBS [v2] RISC-V: Add bext pattern for ZBS - - - 1-- 2023-05-08 Raphael Moreira Zinsly Accepted
RISC-V: Fix CTZ unnecessary sign extension [PR #106888] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] - - - 1-- 2023-05-04 Raphael Moreira Zinsly Accepted
RISC-V: Add bext pattern for ZBS RISC-V: Add bext pattern for ZBS - - - 1-- 2023-05-04 Raphael Moreira Zinsly Accepted
RISC-V: Optimize min/max with SImode sources on 64-bit RISC-V: Optimize min/max with SImode sources on 64-bit - - - 1-- 2022-12-28 Raphael Moreira Zinsly Accepted
[v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] [v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602] - - - 1-- 2022-12-09 Raphael Moreira Zinsly Accepted
RISC-V: Produce better code with complex constants [PR95632] [PR106602] RISC-V: Produce better code with complex constants [PR95632] [PR106602] - - - 1-- 2022-12-07 Raphael Moreira Zinsly Accepted