Show patches with: Submitter = Vineet Gupta       |    Archived = No       |   47 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-17 Vineet Gupta Unresolved
[COMITTED,2/2] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-17 Vineet Gupta Unresolved
RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] - - - -1- 2024-01-16 Vineet Gupta Unresolved
[v2] RISC-V: RVV: add toggle to control vsetvl pass behavior [v2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-16 Vineet Gupta Unresolved
RISC-V: RVV: add toggle to control vsetvl pass behavior RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2023-12-22 Vineet Gupta Unresolved
[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] [Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - - - -1- 2023-11-15 Vineet Gupta Unresolved
[Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [Committed] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - 1 1-- 2023-11-15 Vineet Gupta Accepted
RISC-V: fix vsetvli pass testsuite failure [PR/112447] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - - - -1- 2023-11-15 Vineet Gupta Unresolved
[RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [RESEND,v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1-- 2023-11-15 Vineet Gupta Accepted
[[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls [[Committed] ] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - - 1 1-- 2023-11-01 Vineet Gupta Accepted
RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls - - 1 1-- 2023-10-31 Vineet Gupta Accepted
[v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v3] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - 1 1-- 2023-10-30 Vineet Gupta Accepted
[v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump [v2] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump - - - 1-- 2023-10-30 Vineet Gupta Accepted
[RFC] RISC-V: elide sign extend when expanding cmp_and_jump [RFC] RISC-V: elide sign extend when expanding cmp_and_jump - - - 1-- 2023-10-25 Vineet Gupta Accepted
[COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output [COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output - - - -1- 2023-10-17 Vineet Gupta Unresolved
[v2] RISC-V/testsuite/pr111466.c: update test and expected output [v2] RISC-V/testsuite/pr111466.c: update test and expected output - - - -1- 2023-10-17 Vineet Gupta Unresolved
RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W - - - -1- 2023-10-17 Vineet Gupta Unresolved
[COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests [COMMITTED] RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - 1-- 2023-10-16 Vineet Gupta Accepted
RISC-V/testsuite: add a default march (lacking zfa) to some fp tests RISC-V/testsuite: add a default march (lacking zfa) to some fp tests - - - 1-- 2023-10-15 Vineet Gupta Accepted
[COMMITTED] RISC-V: const: hide mvconst splitter from IRA [COMMITTED] RISC-V: const: hide mvconst splitter from IRA - - - 1-- 2023-10-06 Vineet Gupta Accepted
[v2] RISC-V: const: hide mvconst splitter from IRA [v2] RISC-V: const: hide mvconst splitter from IRA - - - 1-- 2023-10-06 Vineet Gupta Accepted
[RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466] [RFC] expr: don't clear SUBREG_PROMOTED_VAR_P flag for a promoted subreg [target/111466] - - - 1-- 2023-09-28 Vineet Gupta Accepted
[Committed] RISC-V: zicond: Fix opt2 pattern [Committed] RISC-V: zicond: Fix opt2 pattern - - - -1- 2023-09-05 Vineet Gupta Unresolved
[v2] RISC-V: zicond: Fix opt2 pattern [v2] RISC-V: zicond: Fix opt2 pattern - - - -1- 2023-09-01 Vineet Gupta Unresolved
RISC-V: zicond: remove bogus opt2 pattern RISC-V: zicond: remove bogus opt2 pattern - - - -1- 2023-08-30 Vineet Gupta Unresolved
[Committed] RISC-V: Enable Hoist to GCSE simple constants [Committed] RISC-V: Enable Hoist to GCSE simple constants - - - 1-- 2023-08-25 Vineet Gupta Accepted
[v2] RISC-V: Enable Hoist to GCSE simple constants [v2] RISC-V: Enable Hoist to GCSE simple constants - - - 1-- 2023-08-25 Vineet Gupta Accepted
[Committed] RISC-V: output Autovec params explicitly in --help ... [Committed] RISC-V: output Autovec params explicitly in --help ... - - - 1-- 2023-08-22 Vineet Gupta Accepted
RISC-V: output Autovec params explicitly in --help ... RISC-V: output Autovec params explicitly in --help ... - - - 1-- 2023-08-22 Vineet Gupta Accepted
RISC-V: Enable Hoist to GCSE simple constants RISC-V: Enable Hoist to GCSE simple constants - - - 1-- 2023-08-10 Vineet Gupta Accepted
[Committed] RISC-V: optim const DF +0.0 store to mem [PR/110748] [Committed] RISC-V: optim const DF +0.0 store to mem [PR/110748] - - - 1-- 2023-07-22 Vineet Gupta Accepted
[v2] RISC-V: optim const DF +0.0 store to mem [PR/110748] [v2] RISC-V: optim const DF +0.0 store to mem [PR/110748] - - - 1-- 2023-07-21 Vineet Gupta Accepted
RISC-V: optim const DF +0.0 store to mem [PR/110748] RISC-V: optim const DF +0.0 store to mem [PR/110748] - 1 - 1-- 2023-07-21 Vineet Gupta Accepted
RISC-V: improve codegen for repeating large constants [3] RISC-V: improve codegen for repeating large constants [3] - - - 1-- 2023-06-30 Vineet Gupta Accepted
[Committed] testsuite: print any leaking torture options for debugging [Committed] testsuite: print any leaking torture options for debugging - - - 1-- 2023-06-01 Vineet Gupta Accepted
[Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) [Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) - - - 1-- 2023-06-01 Vineet Gupta Accepted
[3/3] testsuite: print any leaking torture options for debugging Unbork testsuite for multlib setups - - - -1- 2023-05-31 Vineet Gupta Unresolved
[2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp Unbork testsuite for multlib setups - - - -1- 2023-05-31 Vineet Gupta Unresolved
[1/3] testsuite: Unbork multilib testing on RISC-V (and any target really) Unbork testsuite for multlib setups - - - 1-- 2023-05-31 Vineet Gupta Accepted
RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] RISC-V: improve codegen for large constants with same 32-bit lo and hi parts [2] - - - 1-- 2023-05-18 Vineet Gupta Accepted
MAINTAINERS: add Vineet Gupta to write after approval MAINTAINERS: add Vineet Gupta to write after approval 1 - - 1-- 2023-04-20 Vineet Gupta Accepted
[v2] expansion: make layout of x_shift*cost[][][] more efficient [v2] expansion: make layout of x_shift*cost[][][] more efficient - - - 1-- 2023-04-18 Vineet Gupta Accepted
expansion: make layout of x_shift*cost[][][] more efficient expansion: make layout of x_shift*cost[][][] more efficient - - - 1-- 2023-04-18 Vineet Gupta Accepted
[v2] riscv: relax splitter restrictions for creating pseudos [v2] riscv: relax splitter restrictions for creating pseudos - - - 1-- 2023-04-18 Vineet Gupta Accepted
riscv: relax splitter restrictions for creating pseudos riscv: relax splitter restrictions for creating pseudos - - - 1-- 2023-04-18 Vineet Gupta Accepted
RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] - 1 - -1- 2023-03-01 Vineet Gupta Repeat Merge
riscv: generate builtin macro for compilation with strict alignment riscv: generate builtin macro for compilation with strict alignment - - - 1-- 2023-01-17 Vineet Gupta Accepted