Show patches with: Submitter = Monk Chiang       |    Archived = No       |   17 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[committed] Add myself to write after approval [committed] Add myself to write after approval - - - 1-- 2024-02-23 Monk Chiang Accepted
RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742] RISC-V: Fix macro fusion for auipc+add, when identifying UNSPEC_AUIPC. [PR113742] - - - -1- 2024-02-05 Monk Chiang Unresolved
[2/2] RISC-V: Add sifive-p450, sifive-p67 to -mcpu [1/2] RISC-V: Support scheduling for sifive p400 series - - - -1- 2024-02-02 Monk Chiang Unresolved
[1/2] RISC-V: Support scheduling for sifive p400 series [1/2] RISC-V: Support scheduling for sifive p400 series - - - -1- 2024-02-02 Monk Chiang Unresolved
[v2] RISC-V: Add minimal support for 7 new unprivileged extensions [v2] RISC-V: Add minimal support for 7 new unprivileged extensions - - - -1- 2024-02-01 Monk Chiang Unresolved
RISC-V: Add minimal support for 7 new unprivileged extensions RISC-V: Add minimal support for 7 new unprivileged extensions - - - -1- 2024-02-01 Monk Chiang Unresolved
[v2] RISC-V: Support scheduling for sifive p600 series [v2] RISC-V: Support scheduling for sifive p600 series - - - -1- 2024-02-01 Monk Chiang Unresolved
RISC-V: Support scheduling for sifive p600 series RISC-V: Support scheduling for sifive p600 series - - - -1- 2024-01-31 Monk Chiang Unresolved
[v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] [v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] - - - -1- 2024-01-24 Monk Chiang Unresolved
[v2] RISC-V: Add split pattern to generate SFB instructions. [PR113095] [v2] RISC-V: Add split pattern to generate SFB instructions. [PR113095] - - - -1- 2024-01-22 Monk Chiang Unresolved
RISC-V: Add split pattern to generate SFB instructions. [PR113095] RISC-V: Add split pattern to generate SFB instructions. [PR113095] - - - -1- 2024-01-19 Monk Chiang Unresolved
match: Do not select to branchless expression when target has movcc pattern [PR113095] match: Do not select to branchless expression when target has movcc pattern [PR113095] - - - -1- 2024-01-17 Monk Chiang Unresolved
[2/2] RISC-V: Implement locality for __builtin_prefetch [1/2] RISC-V: Recognized zihintntl extensions - - - 1-- 2023-07-13 Monk Chiang Accepted
[1/2] RISC-V: Recognized zihintntl extensions [1/2] RISC-V: Recognized zihintntl extensions - - - 1-- 2023-07-13 Monk Chiang Accepted
RISC-V: Remove unnecessary register class. RISC-V: Remove unnecessary register class. - - - 1-- 2023-02-03 Monk Chiang Accepted
RISC-V: Recognized Svinval and Svnapot extensions RISC-V: Recognized Svinval and Svnapot extensions - - - 1-- 2022-10-25 Monk Chiang Accepted
RISC-V: Add type attribute for atomic instructions. RISC-V: Add type attribute for atomic instructions. - - - -1- 2022-10-21 Monk Chiang Unresolved