Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Use merge approach to optimize vector permutation RISC-V: Use merge approach to optimize vector permutation - - - -1- 2023-06-14 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add more SLP tests [V3] RISC-V: Add more SLP tests - - - 1-- 2023-06-13 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Add more SLP tests [V2] RISC-V: Add more SLP tests - - - 1-- 2023-06-13 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix bug of VLA SLP auto-vectorization RISC-V: Fix bug of VLA SLP auto-vectorization - - - -1- 2023-06-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add more SLP tests RISC-V: Add more SLP tests - - - 1-- 2023-06-13 juzhe.zhong@rivai.ai Accepted
RISC-V: Add comments of some functions RISC-V: Add comments of some functions - - - -1- 2023-06-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation [V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add ZVFHMIN block autovec testcase [V2] RISC-V: Add ZVFHMIN block autovec testcase - - - 1-- 2023-06-12 juzhe.zhong@rivai.ai Accepted
RISC-V: Add ZVFHMIN autovec block testcase RISC-V: Add ZVFHMIN autovec block testcase - - - 1-- 2023-06-12 juzhe.zhong@rivai.ai Accepted
[V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control [V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control - - - 1-- 2023-06-12 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV narrow shift right lowering auto-vectorization RISC-V: Add RVV narrow shift right lowering auto-vectorization - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
VECT: Add LEN_MASK_ LOAD/STORE to support flow control for length loop control VECT: Add LEN_MASK_ LOAD/STORE to support flow control for length loop control - - - 1-- 2023-06-11 juzhe.zhong@rivai.ai Accepted
RISC-V: Enable select_vl for RVV auto-vectorization RISC-V: Enable select_vl for RVV auto-vectorization - - - -1- 2023-06-10 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS [V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix V_WHOLE && V_FRACT iterator requirement RISC-V: Fix V_WHOLE && V_FRACT iterator requirement - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS [V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V6] VECT: Add SELECT_VL support [V6] VECT: Add SELECT_VL support - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Add SELECT_VL support [V5] VECT: Add SELECT_VL support - - - -1- 2023-06-08 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Add SELECT_VL support [V4] VECT: Add SELECT_VL support - - - -1- 2023-06-07 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support RVV VLA SLP auto-vectorization [V2] RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-07 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support RVV VLA SLP auto-vectorization RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable SELECT_VL for RVV RISC-V: Enable SELECT_VL for RVV - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support RVV VLA SLP auto-vectorization RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
回复: Re: [PATCH V3] VECT: Add SELECT_VL support 回复: Re: [PATCH V3] VECT: Add SELECT_VL support - - - --1 2023-06-05 juzhe.zhong@rivai.ai Not Applicable
[V3] VECT: Add SELECT_VL support [V3] VECT: Add SELECT_VL support - - - -1- 2023-06-05 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Add SELECT_VL support [V2] VECT: Add SELECT_VL support - - - -1- 2023-06-05 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Move optimization patterns into autovec-opt.md [NFC] RISC-V: Move optimization patterns into autovec-opt.md - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Split arguments of expand_vec_perm RISC-V: Split arguments of expand_vec_perm - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Reorganize riscv-v.cc [NFC] RISC-V: Reorganize riscv-v.cc - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 - - - 1-- 2023-06-04 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Fix warning in predicated.md [V2] RISC-V: Fix warning in predicated.md - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize reverse series index vector RISC-V: Optimize reverse series index vector - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning in predicated.md RISC-V: Fix warning in predicated.md - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid [V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid - - - 1-- 2023-06-02 juzhe.zhong@rivai.ai Accepted
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid - - - 1-- 2023-06-02 juzhe.zhong@rivai.ai Accepted
RISC-V: Add __RISCV_ prefix to VXRM and FRM enum RISC-V: Add __RISCV_ prefix to VXRM and FRM enum - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid - - - 1-- 2023-06-01 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations [V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations - - - 1-- 2023-06-01 juzhe.zhong@rivai.ai Accepted
RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations - - - 1-- 2023-06-01 juzhe.zhong@rivai.ai Accepted
[V3] VECT: Change flow of decrement IV [V3] VECT: Change flow of decrement IV - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization - - - 1-- 2023-06-01 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Support RVV permutation auto-vectorization [V2] RISC-V: Support RVV permutation auto-vectorization - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Change flow of decrement IV [V2] VECT: Change flow of decrement IV - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectoriza… [V2] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectoriza… - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfncvt.rod instruction RISC-V: Remove FRM for vfncvt.rod instruction - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add testcase for vrsub.vi auto-vectorization RISC-V: Add testcase for vrsub.vi auto-vectorization - - - 1-- 2023-05-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Support RVV permutation auto-vectorization RISC-V: Support RVV permutation auto-vectorization - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
VECT: Change flow of decrement IV VECT: Change flow of decrement IV - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix warning in riscv.md [V2] RISC-V: Fix warning in riscv.md - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning in riscv.md RISC-V: Fix warning in riscv.md - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV FNMA auto-vectorization support [V2] RISC-V: Add RVV FNMA auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV FNMA auto-vectorization support RISC-V: Add RVV FNMA auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support [V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support RISC-V: Add floating-point to integer conversion RVV auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant printf of abs-run.c RISC-V: Remove redundant printf of abs-run.c - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV FMA auto-vectorization support [V2] RISC-V: Add RVV FMA auto-vectorization support - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV FMA auto-vectorization support RISC-V: Add RVV FMA auto-vectorization support - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization - - - 1-- 2023-05-26 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Fix zero-scratch-regs-3.c fail [V2] RISC-V: Fix zero-scratch-regs-3.c fail - - - -1- 2023-05-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix zero-scratch-regs-3.c fail RISC-V: Fix zero-scratch-regs-3.c fail - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
VECT: Add SELECT_VL support VECT: Add SELECT_VL support - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
[V17] VECT: Add decrement IV iteration loop control by variable amount support [V17] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-25 juzhe.zhong@rivai.ai Accepted
[V16] VECT: Add decrement IV iteration loop control by variable amount support [V16] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-25 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM [V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM - - - -1- 2023-05-25 juzhe.zhong@rivai.ai Unresolved
[V15] VECT: Add decrement IV iteration loop control by variable amount support [V15] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-25 juzhe.zhong@rivai.ai Accepted
[V14] VECT: Add decrement IV iteration loop control by variable amount support [V14] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-24 juzhe.zhong@rivai.ai Accepted
[V13] VECT: Add decrement IV iteration loop control by variable amount support [V13] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove FRM_REGNUM dependency for rtx conversions RISC-V: Remove FRM_REGNUM dependency for rtx conversions - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add FRM_ prefix to dynamic rounding mode enum RISC-V: Add FRM_ prefix to dynamic rounding mode enum - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2,COMMITTED] RISC-V: Add RVV mask logic auto-vectorization [V2,COMMITTED] RISC-V: Add RVV mask logic auto-vectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV mask logic auto-vectorization RISC-V: Add RVV mask logic auto-vectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Add RVV comparison autovectorization [V5] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Add RVV comparison autovectorization [V4] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect code of reaching inaccessible memory address [V2] RISC-V: Fix incorrect code of reaching inaccessible memory address - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect code of touching inaccessible memory address RISC-V: Fix incorrect code of touching inaccessible memory address - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix magic number of RVV auto-vectorization expander [V2] RISC-V: Fix magic number of RVV auto-vectorization expander - 2 - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix magic number of RVV auto-vectorization expander RISC-V: Fix magic number of RVV auto-vectorization expander - - - -1- 2023-05-24 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add RVV comparison autovectorization [V3] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV comparison autovectorization [V2] RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning of vxrm pattern RISC-V: Fix warning of vxrm pattern - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Refactor the framework of RVV auto-vectorization [V2] RISC-V: Refactor the framework of RVV auto-vectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor the framework of RVV auto-vectorization RISC-V: Refactor the framework of RVV auto-vectorization - - - -1- 2023-05-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add "m_" prefix for private member RISC-V: Add "m_" prefix for private member - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix typo of multiple_rgroup-2.h RISC-V: Fix typo of multiple_rgroup-2.h - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
[V12] VECT: Add decrement IV iteration loop control by variable amount support [V12] VECT: Add decrement IV iteration loop control by variable amount support - - - 1-- 2023-05-22 juzhe.zhong@rivai.ai Accepted
[V13] VECT: Fix bug of multiple-rgroup for length is counting elements [V13] VECT: Fix bug of multiple-rgroup for length is counting elements - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Corrupt patch
RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc RISC-V: Reorganize the code of CONST_VECTOR handling in riscv.cc - - - -1- 2023-05-22 juzhe.zhong@rivai.ai Unresolved
[V12] VECT: Fix issue of multiple-rgroup for length is counting elements [V12] VECT: Fix issue of multiple-rgroup for length is counting elements - - - 1-- 2023-05-22 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV comparison autovectorization RISC-V: Add RVV comparison autovectorization - - - -1- 2023-05-20 juzhe.zhong@rivai.ai Unresolved
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