Show patches with: Archived = No       |   15942 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,1/4] LoongArch: improved target configuration interface LoongArch: target configuration interface update - - - -1- 2023-08-31 Yang Yujie Unresolved
middle-end/111253 - partly revert r11-6508-gabb1b6058c09a7 middle-end/111253 - partly revert r11-6508-gabb1b6058c09a7 - - - 1-- 2023-08-31 Richard Biener Accepted
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
RISC-V: Add Vector cost model framework for RVV RISC-V: Add Vector cost model framework for RVV - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index - - - 1-- 2023-08-31 Ajit Agarwal Accepted
[v1] LoongArch: Optimize fixed-point and floating-point conversion operations. [v1] LoongArch: Optimize fixed-point and floating-point conversion operations. - - - 1-- 2023-08-31 chenglulu Accepted
rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index rs6000: unnecessary clear after vctzlsbb in vec_first_match_or_eos_index - - - 1-- 2023-08-31 Ajit Agarwal Accepted
Fix gcc.dg/tree-ssa/forwprop-42.c Fix gcc.dg/tree-ssa/forwprop-42.c - - - -1- 2023-08-31 Richard Biener Unresolved
testsuite/vect: Make match patterns more accurate. testsuite/vect: Make match patterns more accurate. - - - 1-- 2023-08-31 Robin Dapp Accepted
[v6,4/4] LoongArch: Add Loongson ASX directive builtin function support. Add Loongson SX/ASX instruction support to LoongArch target. - - - 1-- 2023-08-31 Chenghui Pan Accepted
[v6,3/4] LoongArch: Add Loongson ASX base instruction support. Add Loongson SX/ASX instruction support to LoongArch target. - - - 1-- 2023-08-31 Chenghui Pan Accepted
[v6,2/4] LoongArch: Add Loongson SX directive builtin function support. Add Loongson SX/ASX instruction support to LoongArch target. - - - 1-- 2023-08-31 Chenghui Pan Accepted
[v6,1/4] LoongArch: Add Loongson SX base instruction support. Add Loongson SX/ASX instruction support to LoongArch target. - - - 1-- 2023-08-31 Chenghui Pan Accepted
RISC-V: Change vsetvl tail and mask policy to default policy RISC-V: Change vsetvl tail and mask policy to default policy - - - -1- 2023-08-31 Lehua Ding Unresolved
RISC-V: Emit .note.GNU-stack for non-linux target as well RISC-V: Emit .note.GNU-stack for non-linux target as well - - - 1-- 2023-08-31 Kito Cheng Accepted
[13/13,APX,EGPR] Handle vex insns that only support GPR16 (5/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[12/13,APX_EGPR] Handle legacy insns that only support GPR16 (4/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[11/13,APX,EGPR] Handle legacy insns that only support GPR16 (3/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[10/13,APX,EGPR] Handle legacy insns that only support GPR16 (2/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[09/13,APX,EGPR] Handle legacy insn that only support GPR16 (1/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[08/13,APX,EGPR] Handle GPR16 only vector move insns Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[07/13,APX,EGPR] Add backend hook for base_reg_class/index_reg_class. Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[06/13,APX,EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint. Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[05/13,APX,EGPR] Add register and memory constraints that disallow EGPR Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[04/13,APX,EGPR] Add 16 new integer general purpose registers Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[03/13,APX_EGPR] Initial support for APX_F Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[02/13,APX,EGPR] middle-end: Add index_reg_class with insn argument. Support Intel APX EGPR - - - 1-- 2023-08-31 Hongyu Wang Accepted
[01/13,APX,EGPR] middle-end: Add insn argument to base_reg_class Support Intel APX EGPR - - - 1-- 2023-08-31 Hongyu Wang Accepted
[RFC] c++: Diagnose [basic.scope.block]/2 violations even for block externs [PR52953] [RFC] c++: Diagnose [basic.scope.block]/2 violations even for block externs [PR52953] - - - -1- 2023-08-31 Jakub Jelinek Unresolved
c++: Diagnose [basic.scope.block]/2 violations even in compound-stmt of function-try-block [PR52953] c++: Diagnose [basic.scope.block]/2 violations even in compound-stmt of function-try-block [PR52953] - - - -1- 2023-08-31 Jakub Jelinek Unresolved
[v5] LoongArch:Implement 128-bit floating point functions in gcc. [v5] LoongArch:Implement 128-bit floating point functions in gcc. - - - 1-- 2023-08-31 chenxiaolong Accepted
[2/2] c++: Extended diagnostics for P0847R7 (Deducing This) [PR102609] Untitled series #56768 - - - -1- 2023-08-31 waffl3x Unresolved
[2/2,RISC-V] Enalble zcmp for -Os resolve confilct between zcmp multi push/pop and shrink-wrap-separate - - - -1- 2023-08-31 Fei Gao Unresolved
[1/2] allow targets to check shrink-wrap-separate enabled or not resolve confilct between zcmp multi push/pop and shrink-wrap-separate - - - 1-- 2023-08-31 Fei Gao Accepted
[1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609] [1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609] - - - -1- 2023-08-31 waffl3x Unresolved
[committed] arc: Honor SWAP option for lsl16 instruction [committed] arc: Honor SWAP option for lsl16 instruction - - - 1-- 2023-08-31 Claudiu Zissulescu Ianculescu Accepted
[v2] RISC-V: Optimize the MASK opt generation [v2] RISC-V: Optimize the MASK opt generation - - - -1- 2023-08-31 Feng Wang Unresolved
[v4] LoongArch:Implement 128-bit floating point functions in gcc. [v4] LoongArch:Implement 128-bit floating point functions in gcc. - - - 1-- 2023-08-31 chenxiaolong Accepted
[RFC,v2,1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support - - - -1- 2023-08-30 Tsukasa OI Unresolved
rs6000: Update instruction counts to match vec_* calls [PR111228] rs6000: Update instruction counts to match vec_* calls [PR111228] - - - 1-- 2023-08-30 Peter Bergner Accepted
MATCH: extend min_value/max_value match to vectors MATCH: extend min_value/max_value match to vectors - - - -1- 2023-08-30 Andrew Pinski Unresolved
RISC-V: zicond: remove bogus opt2 pattern RISC-V: zicond: remove bogus opt2 pattern - - - -1- 2023-08-30 Vineet Gupta Unresolved
[committed] pru: Add cstore expansion patterns [committed] pru: Add cstore expansion patterns - - - 1-- 2023-08-30 Dimitar Dimitrov Accepted
expmed: Allow extract_bit_field via mem for low-precision modes. expmed: Allow extract_bit_field via mem for low-precision modes. - - - 1-- 2023-08-30 Robin Dapp Accepted
[V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
tree-optimization/111228 - combine two VEC_PERM_EXPRs tree-optimization/111228 - combine two VEC_PERM_EXPRs - - - 1-- 2023-08-30 Richard Biener Accepted
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions - - - -1- 2023-08-30 Lehua Ding Unresolved
test: Add xfail into slp-reduc-7.c for RVV VLA vectorization test: Add xfail into slp-reduc-7.c for RVV VLA vectorization - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
test: Adapt slp-26.c check for RVV test: Adapt slp-26.c check for RVV - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
Adjust costing of emulated vectorized gather/scatter Adjust costing of emulated vectorized gather/scatter - - - 1-- 2023-08-30 liuhongt Accepted
[v3,4/4] ifcvt: Remove obsolete code for subreg handling in noce_convert_multiple_sets ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - -1- 2023-08-30 Manolis Tsamis Unresolved
[v3,3/4] ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_sets ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - -1- 2023-08-30 Manolis Tsamis Unresolved
[v3,2/4] ifcvt: Allow more operations in multiple set if conversion ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - 1-- 2023-08-30 Manolis Tsamis Accepted
[v3,1/4] ifcvt: handle sequences that clobber flags in noce_convert_multiple_sets ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - 1-- 2023-08-30 Manolis Tsamis Accepted
test: Fix XPASS of RVV test: Fix XPASS of RVV - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix vsetvl pass ICE RISC-V: Fix vsetvl pass ICE - - - -1- 2023-08-30 Lehua Ding Unresolved
[8/8] aarch64: Add SVE support for simd clones [PR 96342] [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[PATCH7/8] vect: Add TARGET_SIMD_CLONE_ADJUST_RET_OR_PARAM [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[6/8] vect: Add vector_mode paramater to simd_clone_usable [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[5/8] vect: Use inbranch simdclones in masked loops [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[4/8] vect: don't allow fully masked loops with non-masked simd clones [PR 110485] [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[3/8] vect: Fix vect_get_smallest_scalar_type for simd clones [1/8] parloops: Copy target and optimizations when creating a function clone - - - --1 2023-08-30 Andre Vieira (lists) Not Applicable
[2/8] parloops: Allow poly nit and bound [1/8] parloops: Copy target and optimizations when creating a function clone - - - 1-- 2023-08-30 Andre Vieira (lists) Accepted
[1/8] parloops: Copy target and optimizations when creating a function clone [1/8] parloops: Copy target and optimizations when creating a function clone - - - 1-- 2023-08-30 Andre Vieira (lists) Accepted
Refactor vector HF/BF mode iterators and patterns. Refactor vector HF/BF mode iterators and patterns. - - - -1- 2023-08-30 liuhongt Unresolved
tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914] tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914] - - - -1- 2023-08-30 Jakub Jelinek Unresolved
test: Add xfail for riscv_vector test: Add xfail for riscv_vector - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
[V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
store-merging: Fix up >= 64 bit insertion [PR111015] store-merging: Fix up >= 64 bit insertion [PR111015] - - - -1- 2023-08-30 Jakub Jelinek Unresolved
[V4,2/2] rs6000: use mtvsrws to move sf from si p9 [V4,1/2] rs6000: optimize moving to sf from highpart di - - - 1-- 2023-08-30 Jiufu Guo Accepted
[V4,1/2] rs6000: optimize moving to sf from highpart di [V4,1/2] rs6000: optimize moving to sf from highpart di - - - 1-- 2023-08-30 Jiufu Guo Accepted
[RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support [RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support - - - -1- 2023-08-30 Tsukasa OI Unresolved
RISC-V: Document some -march special cases RISC-V: Document some -march special cases - - - 1-- 2023-08-30 Palmer Dabbelt Accepted
middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
RISC-V: Make sure we get VL REG operand for VLMAX vsetvl RISC-V: Make sure we get VL REG operand for VLMAX vsetvl - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
[v2,4/4] LoongArch: support loongarch*-elf target LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,3/4] LoongArch: add new configure option --with-strict-align-lib LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,2/4] LoongArch: define preprocessing macros "__loongarch_{arch, tune}" LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,1/4] LoongArch: improved target configuration interface LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[V3,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
Bug 111071: fix the subr with -1 to not due to the simplify. Bug 111071: fix the subr with -1 to not due to the simplify. - - - 1-- 2023-08-30 Li, Pan2 via Gcc-patches Accepted
[committed] RISC-V: Use splitter to generate zicond in another case [committed] RISC-V: Use splitter to generate zicond in another case - - - -1- 2023-08-29 Jeff Law Unresolved
[pushed] analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860] [pushed] analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860] - - - -1- 2023-08-29 David Malcolm Unresolved
RFC: Introduce -fhardened to enable security-related flags RFC: Introduce -fhardened to enable security-related flags - - - 1-- 2023-08-29 Marek Polacek Accepted
c++: disallow constinit on functions [PR111173] c++: disallow constinit on functions [PR111173] - - - 1-- 2023-08-29 Marek Polacek Accepted
analyzer: implement reference count checking for CPython plugin [PR107646] analyzer: implement reference count checking for CPython plugin [PR107646] - - - -1- 2023-08-29 Eric Feng Unresolved
OpenMP (C only): omp allocate - handle stack vars, improve diagnostic OpenMP (C only): omp allocate - handle stack vars, improve diagnostic - - - -1- 2023-08-29 Tobias Burnus Unresolved
attribs: Use existing traits for excl_hash_traits attribs: Use existing traits for excl_hash_traits - - - 1-- 2023-08-29 Richard Sandiford Accepted
RFC: RISC-V sign extension dead code elimination RFC: RISC-V sign extension dead code elimination - - - 1-- 2023-08-29 Joern Rennecke Accepted
[pushed] analyzer: improve strdup handling [PR105899] [pushed] analyzer: improve strdup handling [PR105899] - - - -1- 2023-08-29 David Malcolm Unresolved
c++: Check for indirect change of active union member in constexpr [PR101631] c++: Check for indirect change of active union member in constexpr [PR101631] - - - 1-- 2023-08-29 Nathaniel Shead Accepted
libstdc++: Fix -Wunused-parameter warnings libstdc++: Fix -Wunused-parameter warnings - - - --1 2023-08-29 Pekka Seppänen Not Applicable
[COMMITTED] MAINTAINERS: Add myself to write after approval [COMMITTED] MAINTAINERS: Add myself to write after approval - - - 1-- 2023-08-29 Tsukasa OI Accepted
[v1] RISC-V: Fix one ICE for vect test vect-multitypes-5 [v1] RISC-V: Fix one ICE for vect test vect-multitypes-5 - - - 1-- 2023-08-29 Li, Pan2 via Gcc-patches Accepted
RISC-V: Enable movmisalign for VLS modes RISC-V: Enable movmisalign for VLS modes - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove movmisalign pattern for VLA modes RISC-V: Remove movmisalign pattern for VLA modes - - - 1-- 2023-08-29 juzhe.zhong@rivai.ai Accepted
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