Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[V2] RISC-V: Support non-SLP unordered reduction [V2] RISC-V: Support non-SLP unordered reduction - - - -1- 2023-07-17 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add TARGET_MIN_VLEN > 4096 check [V2] RISC-V: Add TARGET_MIN_VLEN > 4096 check - - - 1-- 2023-07-17 juzhe.zhong@rivai.ai Accepted
RISC-V: Add TARGET_MIN_VLEN > 4096 check RISC-V: Add TARGET_MIN_VLEN > 4096 check - - - 1-- 2023-07-17 juzhe.zhong@rivai.ai Accepted
VECT: Add mask_len_fold_left_plus for in-order floating-point reduction VECT: Add mask_len_fold_left_plus for in-order floating-point reduction - - - 1-- 2023-07-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Support non-SLP unordered reduction RISC-V: Support non-SLP unordered reduction - - - -1- 2023-07-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable COND_LEN_FMA auto-vectorization [V2] RISC-V: Enable COND_LEN_FMA auto-vectorization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable COND_LEN_FMA auto-vectorization RISC-V: Enable COND_LEN_FMA auto-vectorization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
[V2] SSA MATH: Support COND_LEN_FMA for floating-point math optimization [V2] SSA MATH: Support COND_LEN_FMA for floating-point math optimization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
SSA MATH: Support COND_LEN_FMA for floating-point math optimization SSA MATH: Support COND_LEN_FMA for floating-point math optimization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support COND_LEN_* patterns [V2] RISC-V: Support COND_LEN_* patterns - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply COND_LEN_* into vectorizable_operation [V4] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply COND_LEN_* into vectorizable_operation [V3] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply COND_LEN_* into vectorizable_operation [V2] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization [V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support integer mult highpart auto-vectorization RISC-V: Support integer mult highpart auto-vectorization - - - 1-- 2023-07-12 juzhe.zhong@rivai.ai Accepted
RISC-V: Support COND_LEN_* patterns RISC-V: Support COND_LEN_* patterns - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
VECT: Apply COND_LEN_* into vectorizable_operation VECT: Apply COND_LEN_* into vectorizable_operation - - - 1-- 2023-07-12 juzhe.zhong@rivai.ai Accepted
RISC-V: Optimize permutation codegen with vcompress RISC-V: Optimize permutation codegen with vcompress - - - -1- 2023-07-11 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Add COND_LEN_* operations for loop control with length targets [V2] VECT: Add COND_LEN_* operations for loop control with length targets - - - 1-- 2023-07-10 juzhe.zhong@rivai.ai Accepted
[v2] GCSE: Export 'insert_insn_end_basic_block' as global function [v2] GCSE: Export 'insert_insn_end_basic_block' as global function - - - 1-- 2023-07-10 juzhe.zhong@rivai.ai Accepted
GCSE: Export 'insert_insn_end_basic_block' as global function GCSE: Export 'insert_insn_end_basic_block' as global function - - - 1-- 2023-07-10 juzhe.zhong@rivai.ai Accepted
GCSE: Export add_label_notes as global function GCSE: Export add_label_notes as global function - - - 1-- 2023-07-10 juzhe.zhong@rivai.ai Accepted
[V5] RISC-V: Support gather_load/scatter RVV auto-vectorization [V5] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Support gather_load/scatter RVV auto-vectorization [V4] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
VECT: Add COND_LEN_* operations for loop control with length targets VECT: Add COND_LEN_* operations for loop control with length targets - - - 1-- 2023-07-07 juzhe.zhong@rivai.ai Accepted
[V3] RISC-V: Support gather_load/scatter RVV auto-vectorization [V3] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support gather_load/scatter RVV auto-vectorization [V2] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. [V2] VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
[v1] RISC-V: Support gather_load/scatter RVV auto-vectorization [v1] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-05 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V4] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V3] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V2] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[VSETVL,PASS] RISC-V: Optimize local AVL propagation [VSETVL,PASS] RISC-V: Optimize local AVL propagation - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V7] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V7] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments [V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V6] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V6] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - 1-- 2023-06-30 juzhe.zhong@rivai.ai Accepted
[V5] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V5] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V4] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V4] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V3] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V3] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V2] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V2] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI [V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwmacc combine lowering RISC-V: Support vfwmacc combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwmul.vv combine lowering RISC-V: Support vfwmul.vv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering [V2] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix bug of pre-calculated const vector mask [V2] RISC-V: Fix bug of pre-calculated const vector mask - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of pre-calculated const vector mask RISC-V: Fix bug of pre-calculated const vector mask - - - -1- 2023-06-27 juzhe.zhong@rivai.ai Unresolved
[V4] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V4] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-27 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support const vector expansion with step vector with base != 0 [V2] RISC-V: Support const vector expansion with step vector with base != 0 - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
[V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
[V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
[V2] GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE} [V2] GIMPLE_FOLD: Fix gimple fold for LEN_{MASK}_{LOAD,STORE} - - - 1-- 2023-06-26 juzhe.zhong@rivai.ai Accepted
[V3] DSE: Add LEN_MASK_STORE analysis into DSE and fix LEN_STORE [V3] DSE: Add LEN_MASK_STORE analysis into DSE and fix LEN_STORE - - - 1-- 2023-06-26 juzhe.zhong@rivai.ai Accepted
RISC-V: Enhance RVV VLA SLP auto-vectorization RISC-V: Enhance RVV VLA SLP auto-vectorization - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant vcond patterns RISC-V: Remove redundant vcond patterns - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
SSCV: Add LEN_MASK_STORE into SCCVN SSCV: Add LEN_MASK_STORE into SCCVN - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
SCCVN: Fix repeating variable name "len" SCCVN: Fix repeating variable name "len" - - - 1-- 2023-06-26 juzhe.zhong@rivai.ai Accepted
[V2] DSE: Add LEN_MASK_STORE analysis into DSE [V2] DSE: Add LEN_MASK_STORE analysis into DSE - - - 1-- 2023-06-26 juzhe.zhong@rivai.ai Accepted
GIMPLE_FOLD: Fix gimple fold for LEN_MASK_{LOAD,STORE} GIMPLE_FOLD: Fix gimple fold for LEN_MASK_{LOAD,STORE} - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store} [V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable len_mask{load, store} and remove len_{load, store} RISC-V: Enable len_mask{load, store} and remove len_{load, store} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
internal-fn: Fix bug of BIAS argument index internal-fn: Fix bug of BIAS argument index - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
[V2] LOOP IVOPTS: Apply LEN_MASK_{LOAD,STORE} [V2] LOOP IVOPTS: Apply LEN_MASK_{LOAD,STORE} - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
DSE: Add LEN_MASK_STORE analysis into DSE DSE: Add LEN_MASK_STORE analysis into DSE - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
IVOPTS: Add LEN_MASK_{LOAD, STORE} into 'get_alias_ptr_type_for_ptr_address' IVOPTS: Add LEN_MASK_{LOAD, STORE} into 'get_alias_ptr_type_for_ptr_address' - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
SSA ALIAS: Apply LEN_MASK_STORE to 'ref_maybe_used_by_call_p_1' SSA ALIAS: Apply LEN_MASK_STORE to 'ref_maybe_used_by_call_p_1' - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
LOOP IVOPTS: Apply LEN_MASK_{LOAD,STORE} LOOP IVOPTS: Apply LEN_MASK_{LOAD,STORE} - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
SSA ALIAS: Apply LEN_MASK_{LOAD, STORE} into SSA alias analysis SSA ALIAS: Apply LEN_MASK_{LOAD, STORE} into SSA alias analysis - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
GIMPLE_FOLD: Apply LEN_MASK_{LOAD,STORE} into GIMPLE_FOLD GIMPLE_FOLD: Apply LEN_MASK_{LOAD,STORE} into GIMPLE_FOLD - - - 1-- 2023-06-23 juzhe.zhong@rivai.ai Accepted
[V6] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V6] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-22 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V5] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor the integer ternary autovec pattern RISC-V: Refactor the integer ternary autovec pattern - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support RVV floating-point auto-vectorization [V3] RISC-V: Support RVV floating-point auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V4] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support RVV floating-point auto-vectorization [V2] RISC-V: Support RVV floating-point auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
: [NFC] Move can_vec_mask_load_store_p and get_len_load_store_mode from "optabs-query" into "optabs… : [NFC] Move can_vec_mask_load_store_p and get_len_load_store_mode from "optabs-query" into "optabs… - - - 1-- 2023-06-21 juzhe.zhong@rivai.ai Accepted
RISC-V: Support RVV floating-point ternary auto-vectorization RISC-V: Support RVV floating-point ternary auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V3] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V2] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Optimize codegen of VLA SLP [V3] RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize codegen of VLA SLP [V2] RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize codegen of VLA SLP RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix fails of testcases RISC-V: Fix fails of testcases - - - -1- 2023-06-19 juzhe.zhong@rivai.ai Unresolved
VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS modes for GNU vectors RISC-V: Add VLS modes for GNU vectors - - - -1- 2023-06-18 juzhe.zhong@rivai.ai Unresolved
[V7] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs [V7] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs - - - 1-- 2023-06-17 juzhe.zhong@rivai.ai Accepted
[V6] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs [V6] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs - - - 1-- 2023-06-16 juzhe.zhong@rivai.ai Accepted
[V5] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs [V5] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs - - - 1-- 2023-06-16 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix VL operand bug in VSETVL PASS[PR110264] RISC-V: Fix VL operand bug in VSETVL PASS[PR110264] - - - 1-- 2023-06-16 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix PR 110264 RISC-V: Fix PR 110264 - - - 1-- 2023-06-16 juzhe.zhong@rivai.ai Accepted
[V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs [V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs - - - 1-- 2023-06-15 juzhe.zhong@rivai.ai Accepted
[V3] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs [V3] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs - - - 1-- 2023-06-15 juzhe.zhong@rivai.ai Accepted
回复: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] 回复: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] - - - --1 2023-06-14 juzhe.zhong@rivai.ai Not Applicable
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