Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |    Archived = No       |   636 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[V2] RISC-V: Support gather_load/scatter RVV auto-vectorization [V2] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. [V2] VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. VECT: Fix ICE of variable stride on strieded load/store with SELECT_VL loop control. - - - -1- 2023-07-06 juzhe.zhong@rivai.ai Unresolved
[v1] RISC-V: Support gather_load/scatter RVV auto-vectorization [v1] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-05 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V5] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V4] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V3] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer [V2] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into vectorizer - - - -1- 2023-07-04 juzhe.zhong@rivai.ai Unresolved
[VSETVL,PASS] RISC-V: Optimize local AVL propagation [VSETVL,PASS] RISC-V: Optimize local AVL propagation - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V7] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V7] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments [V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V6] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V6] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-07-03 juzhe.zhong@rivai.ai Unresolved
[V5] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V5] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V4] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V4] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V3] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V3] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
[V2] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern [V2] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI [V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwmacc combine lowering RISC-V: Support vfwmacc combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vfwmul.vv combine lowering RISC-V: Support vfwmul.vv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering [V2] RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering RISC-V: Support floating-point vfwadd/vfwsub vv/wv combine lowering - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix bug of pre-calculated const vector mask [V2] RISC-V: Fix bug of pre-calculated const vector mask - - - -1- 2023-06-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of pre-calculated const vector mask RISC-V: Fix bug of pre-calculated const vector mask - - - -1- 2023-06-27 juzhe.zhong@rivai.ai Unresolved
[V4] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V4] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-27 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support const vector expansion with step vector with base != 0 [V2] RISC-V: Support const vector expansion with step vector with base != 0 - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
[V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V3] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
[V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE [V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enhance RVV VLA SLP auto-vectorization RISC-V: Enhance RVV VLA SLP auto-vectorization - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant vcond patterns RISC-V: Remove redundant vcond patterns - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
SSCV: Add LEN_MASK_STORE into SCCVN SSCV: Add LEN_MASK_STORE into SCCVN - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
GIMPLE_FOLD: Fix gimple fold for LEN_MASK_{LOAD,STORE} GIMPLE_FOLD: Fix gimple fold for LEN_MASK_{LOAD,STORE} - - - -1- 2023-06-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store} [V2] RISC-V: Enable len_mask{load, store} and remove len_{load, store} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable len_mask{load, store} and remove len_{load, store} RISC-V: Enable len_mask{load, store} and remove len_{load, store} - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
internal-fn: Fix bug of BIAS argument index internal-fn: Fix bug of BIAS argument index - - - -1- 2023-06-25 juzhe.zhong@rivai.ai Unresolved
[V6] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V6] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-22 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V5] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor the integer ternary autovec pattern RISC-V: Refactor the integer ternary autovec pattern - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support RVV floating-point auto-vectorization [V3] RISC-V: Support RVV floating-point auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V4] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support RVV floating-point auto-vectorization [V2] RISC-V: Support RVV floating-point auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support RVV floating-point ternary auto-vectorization RISC-V: Support RVV floating-point ternary auto-vectorization - - - -1- 2023-06-21 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V3] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer [V2] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Optimize codegen of VLA SLP [V3] RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize codegen of VLA SLP [V2] RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize codegen of VLA SLP RISC-V: Optimize codegen of VLA SLP - - - -1- 2023-06-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix fails of testcases RISC-V: Fix fails of testcases - - - -1- 2023-06-19 juzhe.zhong@rivai.ai Unresolved
VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer - - - -1- 2023-06-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS modes for GNU vectors RISC-V: Add VLS modes for GNU vectors - - - -1- 2023-06-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Use merge approach to optimize vector permutation RISC-V: Use merge approach to optimize vector permutation - - - -1- 2023-06-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of VLA SLP auto-vectorization RISC-V: Fix bug of VLA SLP auto-vectorization - - - -1- 2023-06-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add comments of some functions RISC-V: Add comments of some functions - - - -1- 2023-06-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation [V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV narrow shift right lowering auto-vectorization RISC-V: Add RVV narrow shift right lowering auto-vectorization - - - -1- 2023-06-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable select_vl for RVV auto-vectorization RISC-V: Enable select_vl for RVV auto-vectorization - - - -1- 2023-06-10 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS [V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix V_WHOLE && V_FRACT iterator requirement RISC-V: Fix V_WHOLE && V_FRACT iterator requirement - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS [V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V6] VECT: Add SELECT_VL support [V6] VECT: Add SELECT_VL support - - - -1- 2023-06-09 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Add SELECT_VL support [V5] VECT: Add SELECT_VL support - - - -1- 2023-06-08 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Add SELECT_VL support [V4] VECT: Add SELECT_VL support - - - -1- 2023-06-07 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support RVV VLA SLP auto-vectorization [V2] RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-07 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support RVV VLA SLP auto-vectorization RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable SELECT_VL for RVV RISC-V: Enable SELECT_VL for RVV - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization [V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support RVV VLA SLP auto-vectorization RISC-V: Support RVV VLA SLP auto-vectorization - - - -1- 2023-06-06 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Add SELECT_VL support [V3] VECT: Add SELECT_VL support - - - -1- 2023-06-05 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Add SELECT_VL support [V2] VECT: Add SELECT_VL support - - - -1- 2023-06-05 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Move optimization patterns into autovec-opt.md [NFC] RISC-V: Move optimization patterns into autovec-opt.md - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Split arguments of expand_vec_perm RISC-V: Split arguments of expand_vec_perm - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Reorganize riscv-v.cc [NFC] RISC-V: Reorganize riscv-v.cc - - - -1- 2023-06-04 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix warning in predicated.md [V2] RISC-V: Fix warning in predicated.md - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize reverse series index vector RISC-V: Optimize reverse series index vector - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning in predicated.md RISC-V: Fix warning in predicated.md - - - -1- 2023-06-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add __RISCV_ prefix to VXRM and FRM enum RISC-V: Add __RISCV_ prefix to VXRM and FRM enum - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Change flow of decrement IV [V3] VECT: Change flow of decrement IV - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support RVV permutation auto-vectorization [V2] RISC-V: Support RVV permutation auto-vectorization - - - -1- 2023-06-01 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Change flow of decrement IV [V2] VECT: Change flow of decrement IV - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectoriza… [V2] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectoriza… - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfncvt.rod instruction RISC-V: Remove FRM for vfncvt.rod instruction - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion) - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion) - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Support RVV permutation auto-vectorization RISC-V: Support RVV permutation auto-vectorization - - - -1- 2023-05-31 juzhe.zhong@rivai.ai Unresolved
VECT: Change flow of decrement IV VECT: Change flow of decrement IV - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix warning in riscv.md [V2] RISC-V: Fix warning in riscv.md - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix warning in riscv.md RISC-V: Fix warning in riscv.md - - - -1- 2023-05-30 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add RVV FNMA auto-vectorization support [V2] RISC-V: Add RVV FNMA auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV FNMA auto-vectorization support RISC-V: Add RVV FNMA auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support [V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support RISC-V: Add floating-point to integer conversion RVV auto-vectorization support - - - -1- 2023-05-29 juzhe.zhong@rivai.ai Unresolved
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