Show patches with: Submitter = juzhe.zhong@rivai.ai       |    State = Action Required       |    Archived = No       |   636 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Support Dynamic LMUL Cost model RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix Dynamic LMUL compile option RISC-V: Fix Dynamic LMUL compile option - - - -1- 2023-09-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable VECT_COMPARE_COSTS by default RISC-V: Enable VECT_COMPARE_COSTS by default - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add Vector cost model framework for RVV RISC-V: Add Vector cost model framework for RVV - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
[V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
test: Adapt slp-26.c check for RVV test: Adapt slp-26.c check for RVV - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Make sure we get VL REG operand for VLMAX vsetvl RISC-V: Make sure we get VL REG operand for VLMAX vsetvl - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable movmisalign for VLS modes RISC-V: Enable movmisalign for VLS modes - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ASM check of vlmax_switch_vtype-16.c RISC-V: Fix ASM check of vlmax_switch_vtype-16.c - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix AVL/VL get ICE[VSETVL PASS] RISC-V: Fix AVL/VL get ICE[VSETVL PASS] - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V4] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix uninitialized probability for GIMPLE IR tests RISC-V: Fix uninitialized probability for GIMPLE IR tests - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V3] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) block [V2] RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) block - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disable user vsetvl fusion into EMPTY block RISC-V: Disable user vsetvl fusion into EMPTY block - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V2] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable vec_init testsuite for RVV VLA vectorization RISC-V: Enable vec_init testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL test failures RISC-V: Fix VSETVL test failures - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS [V3] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS - - - -1- 2023-08-25 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization [V2] RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization - - - -1- 2023-08-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorization - - - -1- 2023-08-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS [V2] RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS - - - -1- 2023-08-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix potential ICE of global vsetvl elimination RISC-V: Fix potential ICE of global vsetvl elimination - - - -1- 2023-08-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix gather_load_run-12.c test RISC-V: Fix gather_load_run-12.c test - - - -1- 2023-08-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Adapt live-1.c testcase RISC-V: Adapt live-1.c testcase - - - -1- 2023-08-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Clang format riscv-vsetvl.cc[NFC] RISC-V: Clang format riscv-vsetvl.cc[NFC] - - - -1- 2023-08-22 juzhe.zhong@rivai.ai Unresolved
VECT: Add LEN_FOLD_EXTRACT_LAST pattern VECT: Add LEN_FOLD_EXTRACT_LAST pattern - - - -1- 2023-08-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASS - - - -1- 2023-08-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases - - - -1- 2023-08-16 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support MASK_LEN_{LOAD_LANES,STORE_LANES} [V2] RISC-V: Support MASK_LEN_{LOAD_LANES,STORE_LANES} - - - -1- 2023-08-16 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply MASK_LEN_{LOAD_LANES, STORE_LANES} into vectorizer [V2] VECT: Apply MASK_LEN_{LOAD_LANES, STORE_LANES} into vectorizer - - - -1- 2023-08-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support MASK_LEN_{LOAD_LANES,STORE_LANES} RISC-V: Support MASK_LEN_{LOAD_LANES,STORE_LANES} - - - -1- 2023-08-14 juzhe.zhong@rivai.ai Unresolved
VECT: Apply MASK_LEN_{LOAD_LANES, STORE_LANES} into vectorizer VECT: Apply MASK_LEN_{LOAD_LANES, STORE_LANES} into vectorizer - - - -1- 2023-08-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix autovec_length_operand predicate[PR110989] RISC-V: Fix autovec_length_operand predicate[PR110989] - - - -1- 2023-08-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add TAREGT_VECTOR check into VLS modes RISC-V: Add TAREGT_VECTOR check into VLS modes - - - -1- 2023-08-12 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Fix ICE on MASK_LEN_{LOAD, STORE} when no LEN recorded[PR110989] [V2] VECT: Fix ICE on MASK_LEN_{LOAD, STORE} when no LEN recorded[PR110989] - - - -1- 2023-08-11 juzhe.zhong@rivai.ai Unresolved
VECT: Fix ICE on MASK_LEN_{LOAD, STORE} when no LEN recorded[PR110989] VECT: Fix ICE on MASK_LEN_{LOAD, STORE} when no LEN recorded[PR110989] - - - -1- 2023-08-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Allow CONST_VECTOR for VLS modes [V2] RISC-V: Allow CONST_VECTOR for VLS modes - - - -1- 2023-08-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix vec_series expander[PR110985] RISC-V: Fix vec_series expander[PR110985] - - - -1- 2023-08-11 juzhe.zhong@rivai.ai Unresolved
VECT: Add vec_mask_len_{load_lanes,store_lanes} patterns VECT: Add vec_mask_len_{load_lanes,store_lanes} patterns - - - -1- 2023-08-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support TU for integer ternary OP[PR110964] RISC-V: Support TU for integer ternary OP[PR110964] - - - -1- 2023-08-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add missing modes to the iterators RISC-V: Add missing modes to the iterators - - - -1- 2023-08-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support NPATTERNS = 1 stepped vector[PR110950] RISC-V: Support NPATTERNS = 1 stepped vector[PR110950] - - - -1- 2023-08-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VLMAX AVL incorrect local anticipate [VSETVL PASS] RISC-V: Fix VLMAX AVL incorrect local anticipate [VSETVL PASS] - - - -1- 2023-08-09 juzhe.zhong@rivai.ai Unresolved
VECT: Support loop len control on EXTRACT_LAST vectorization VECT: Support loop len control on EXTRACT_LAST vectorization - - - -1- 2023-08-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow CONST_VECTOR for VLS modes. RISC-V: Allow CONST_VECTOR for VLS modes. - - - -1- 2023-08-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support neg VLS auto-vectorization RISC-V: Support neg VLS auto-vectorization - - - -1- 2023-08-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS shift vectorization RISC-V: Support VLS shift vectorization - - - -1- 2023-08-08 juzhe.zhong@rivai.ai Unresolved
tree-optimization/110897 - Fix missed vectorization of shift on both RISC-V and aarch64 tree-optimization/110897 - Fix missed vectorization of shift on both RISC-V and aarch64 - - - -1- 2023-08-07 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Support CALL vectorization for COND_LEN_* [V4] VECT: Support CALL vectorization for COND_LEN_* - - - -1- 2023-08-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS basic operation auto-vectorization RISC-V: Support VLS basic operation auto-vectorization - - - -1- 2023-08-07 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Support CALL vectorization for COND_LEN_* [V4] VECT: Support CALL vectorization for COND_LEN_* - - - -1- 2023-08-03 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support CALL conditional autovec patterns [V2] RISC-V: Support CALL conditional autovec patterns - - - -1- 2023-08-03 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Support CALL vectorization for COND_LEN_* [V3] VECT: Support CALL vectorization for COND_LEN_* - - - -1- 2023-08-01 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support POPCOUNT auto-vectorization [V2] RISC-V: Support POPCOUNT auto-vectorization - - - -1- 2023-07-31 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Fix bug of get_mask_mode [committed] RISC-V: Fix bug of get_mask_mode - - - -1- 2023-07-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support POPCOUNT auto-vectorization RISC-V: Support POPCOUNT auto-vectorization - - - -1- 2023-07-31 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable basic VLS auto-vectorization [V2] RISC-V: Enable basic VLS auto-vectorization - - - -1- 2023-07-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable basic VLS auto-vectorization RISC-V: Enable basic VLS auto-vectorization - - - -1- 2023-07-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support CALL conditional autovec patterns RISC-V: Support CALL conditional autovec patterns - - - -1- 2023-07-28 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support CALL vectorization for COND_LEN_* [V2] VECT: Support CALL vectorization for COND_LEN_* - - - -1- 2023-07-28 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Enable basic VLS modes support [V4] RISC-V: Enable basic VLS modes support - - - -1- 2023-07-27 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Enable basic VLS modes support [V3] RISC-V: Enable basic VLS modes support - - - -1- 2023-07-27 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable basic VLS modes support [V2] RISC-V: Enable basic VLS modes support - - - -1- 2023-07-27 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable basic VLS modes support RISC-V: Enable basic VLS modes support - - - -1- 2023-07-25 juzhe.zhong@rivai.ai Unresolved
internal-fn: Refine macro define of COND_* and COND_LEN_* internal functions internal-fn: Refine macro define of COND_* and COND_LEN_* internal functions - - - -1- 2023-07-25 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Support floating-point in-order reduction for length loop control [V4] VECT: Support floating-point in-order reduction for length loop control - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Support floating-point in-order reduction for length loop control [V3] VECT: Support floating-point in-order reduction for length loop control - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support floating-point in-order reduction for length loop control [V2] VECT: Support floating-point in-order reduction for length loop control - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Fix redundant variable declaration. [committed] RISC-V: Fix redundant variable declaration. - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
cleanup: Change condition order cleanup: Change condition order - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
cleanup: make all cond_len_* and mask_len_* consistent on the order of mask and len cleanup: make all cond_len_* and mask_len_* consistent on the order of mask and len - - - -1- 2023-07-21 juzhe.zhong@rivai.ai Unresolved
cleanup: Change LEN_MASK into MASK_LEN cleanup: Change LEN_MASK into MASK_LEN - - - -1- 2023-07-20 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support in-order floating-point reduction [V2] RISC-V: Support in-order floating-point reduction - - - -1- 2023-07-20 juzhe.zhong@rivai.ai Unresolved
CODE STRUCTURE: Refine codes in Vectorizer CODE STRUCTURE: Refine codes in Vectorizer - - - -1- 2023-07-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support in-order floating-point reduction RISC-V: Support in-order floating-point reduction - - - -1- 2023-07-20 juzhe.zhong@rivai.ai Unresolved
VECT: Support floating-point in-order reduction for length loop control VECT: Support floating-point in-order reduction for length loop control - - - -1- 2023-07-20 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Refactor RVV machine modes [V3] RISC-V: Refactor RVV machine modes - - - -1- 2023-07-19 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Refactor RVV machine modes [V2] RISC-V: Refactor RVV machine modes - - - -1- 2023-07-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor RVV machine modes RISC-V: Refactor RVV machine modes - - - -1- 2023-07-19 juzhe.zhong@rivai.ai Unresolved
MAINTAINERS: Add myself as riscv port reviewer. MAINTAINERS: Add myself as riscv port reviewer. - - - -1- 2023-07-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable SLP un-order reduction [V2] RISC-V: Enable SLP un-order reduction - - - -1- 2023-07-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable SLP un-order reduction RISC-V: Enable SLP un-order reduction - - - -1- 2023-07-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support non-SLP unordered reduction [V2] RISC-V: Support non-SLP unordered reduction - - - -1- 2023-07-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support non-SLP unordered reduction RISC-V: Support non-SLP unordered reduction - - - -1- 2023-07-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable COND_LEN_FMA auto-vectorization [V2] RISC-V: Enable COND_LEN_FMA auto-vectorization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable COND_LEN_FMA auto-vectorization RISC-V: Enable COND_LEN_FMA auto-vectorization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
[V2] SSA MATH: Support COND_LEN_FMA for floating-point math optimization [V2] SSA MATH: Support COND_LEN_FMA for floating-point math optimization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
SSA MATH: Support COND_LEN_FMA for floating-point math optimization SSA MATH: Support COND_LEN_FMA for floating-point math optimization - - - -1- 2023-07-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support COND_LEN_* patterns [V2] RISC-V: Support COND_LEN_* patterns - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Apply COND_LEN_* into vectorizable_operation [V4] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V3] VECT: Apply COND_LEN_* into vectorizable_operation [V3] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Apply COND_LEN_* into vectorizable_operation [V2] VECT: Apply COND_LEN_* into vectorizable_operation - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
[V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization [V7] RISC-V: RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support COND_LEN_* patterns RISC-V: Support COND_LEN_* patterns - - - -1- 2023-07-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize permutation codegen with vcompress RISC-V: Optimize permutation codegen with vcompress - - - -1- 2023-07-11 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Support gather_load/scatter RVV auto-vectorization [V5] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Support gather_load/scatter RVV auto-vectorization [V4] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support gather_load/scatter RVV auto-vectorization [V3] RISC-V: Support gather_load/scatter RVV auto-vectorization - - - -1- 2023-07-07 juzhe.zhong@rivai.ai Unresolved
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