Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
DSE: Fix ICE when the mode with access_size don't exist on the target[PR111590] DSE: Fix ICE when the mode with access_size don't exist on the target[PR111590] - - - 1-- 2023-09-26 juzhe.zhong@rivai.ai Accepted
[V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] [V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] [V2] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] MATCH: Optimize COND_ADD reduction pattern [V2] MATCH: Optimize COND_ADD reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] MATCH: Optimize COND_ADD_LEN reduction pattern [V2] MATCH: Optimize COND_ADD_LEN reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V3] MATCH: Optimize COND_ADD_LEN reduction pattern [V3] MATCH: Optimize COND_ADD_LEN reduction pattern - - - 1-- 2023-09-26 juzhe.zhong@rivai.ai Accepted
MATCH: Optimize COND_ADD reduction pattern MATCH: Optimize COND_ADD reduction pattern - - - -1- 2023-09-26 juzhe.zhong@rivai.ai Unresolved
[V2] MATCH: Optimize COND_ADD_LEN reduction pattern [V2] MATCH: Optimize COND_ADD_LEN reduction pattern - - - 1-- 2023-09-26 juzhe.zhong@rivai.ai Accepted
MATCH: Optimize COND_ADD_LEN reduction pattern MATCH: Optimize COND_ADD_LEN reduction pattern - - - 1-- 2023-09-26 juzhe.zhong@rivai.ai Accepted
RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590] - - - 1-- 2023-09-26 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548] RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548] - - - -1- 2023-09-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support full coverage VLS combine support [Committed] RISC-V: Support full coverage VLS combine support - - - -1- 2023-09-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add VLS unary combine patterns [Committed] RISC-V: Add VLS unary combine patterns - - - -1- 2023-09-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove @ of vec_duplicate pattern [Committed] RISC-V: Remove @ of vec_duplicate pattern - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS conditional patterns support RISC-V: Add VLS conditional patterns support - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add VLS integer ABS support [Committed] RISC-V: Add VLS integer ABS support - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add more VLS unary tests [Committed] RISC-V: Add more VLS unary tests - - - 1-- 2023-09-21 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Support VLS mult high [Committed] RISC-V: Support VLS mult high - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix SUBREG move of VLS mode[PR111486] RISC-V: Fix SUBREG move of VLS mode[PR111486] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS INT <-> FP conversions [Committed] RISC-V: Support VLS INT <-> FP conversions - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[Committed,V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751] [Committed,V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751] - - - 1-- 2023-09-20 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Support VLS floating-point extend/truncate [Committed] RISC-V: Support VLS floating-point extend/truncate - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] - - - 1-- 2023-09-20 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator [Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add FNMS floating-point VLS tests RISC-V: Add FNMS floating-point VLS tests - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS unary floating-point patterns [Committed] RISC-V: Support VLS unary floating-point patterns - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization [Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization [Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix RVV can change mode class bug [V2] RISC-V: Fix RVV can change mode class bug - - - 1-- 2023-09-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix RVV can change mode class bug RISC-V: Fix RVV can change mode class bug - - - 1-- 2023-09-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove redundant vec_duplicate pattern RISC-V: Remove redundant vec_duplicate pattern - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix bogus FAILs of vsetvl testcases [Committed] RISC-V: Fix bogus FAILs of vsetvl testcases - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS reduction [Committed] RISC-V: Support VLS reduction - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VSETVL PASS fusion bug [Committed] RISC-V: Fix VSETVL PASS fusion bug - - - 1-- 2023-09-18 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] [Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[V3] internal-fn: Support undefined rtx for uninitialized SSA_NAME [V3] internal-fn: Support undefined rtx for uninitialized SSA_NAME - - - 1-- 2023-09-18 juzhe.zhong@rivai.ai Accepted
[V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME [V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME - - - 1-- 2023-09-17 juzhe.zhong@rivai.ai Accepted
RISC-V: Support VLS modes reduction[PR111153] RISC-V: Support VLS modes reduction[PR111153] - - - -1- 2023-09-17 juzhe.zhong@rivai.ai Unresolved
internal-fn: Convert uninitialized SSA_NAME into SCRATCH rtx[PR110751] internal-fn: Convert uninitialized SSA_NAME into SCRATCH rtx[PR110751] - - - 1-- 2023-09-16 juzhe.zhong@rivai.ai Accepted
test: Block SLP check of slp-35.c for vect_strided5 test: Block SLP check of slp-35.c for vect_strided5 - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
test: Block SLP check of slp-34.c for vect_strided5 test: Block SLP check of slp-34.c for vect_strided5 - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
test: Block vect_strided5 for slp-34-big-array.c SLP check test: Block vect_strided5 for slp-34-big-array.c SLP check - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
test: Isolate slp-1.c check of target supports vect_strided5 test: Isolate slp-1.c check of target supports vect_strided5 - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
test: Block slp-16.c check for target support vect_strided6 test: Block slp-16.c check for target support vect_strided6 - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
test: Remove XPASS for RISCV test: Remove XPASS for RISCV - - - 1-- 2023-09-15 juzhe.zhong@rivai.ai Accepted
RISC-V: Support VLS modes vec_init auto-vectorization RISC-V: Support VLS modes vec_init auto-vectorization - - - -1- 2023-09-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes mask operations RISC-V: Support VLS modes mask operations - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V4] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V3] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Format VSETVL PASS code [Committed] RISC-V: Format VSETVL PASS code - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix ICE in get_avl_or_vl_reg [V3] RISC-V: Fix ICE in get_avl_or_vl_reg - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix ICE in get_avl_or_vl_reg [V2] RISC-V: Fix ICE in get_avl_or_vl_reg - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE in get_avl_or_vl_reg[PR111395] RISC-V: Fix ICE in get_avl_or_vl_reg[PR111395] - - - -1- 2023-09-14 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Expand VLS mode to scalar mode move[PR111391] [V2] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Expand VLS mode to scalar mode move[PR111391] RISC-V: Expand VLS mode to scalar mode move[PR111391] - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization RISC-V: Support VLS modes VEC_EXTRACT auto-vectorization - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Remove redundant ABI test [committed] RISC-V: Remove redundant ABI test - - - -1- 2023-09-13 juzhe.zhong@rivai.ai Repeat Merge
[V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] [V2] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] RISC-V: Support VECTOR BOOL vcond_mask optab[PR111337] - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V5] RISC-V: Support Dynamic LMUL Cost model [V5] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Support Dynamic LMUL Cost model [V4] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-12 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support Dynamic LMUL Cost model [V3] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support Dynamic LMUL Cost model [V2] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove redundant functions RISC-V: Remove redundant functions - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Use dominance analysis in global vsetvl elimination RISC-V: Use dominance analysis in global vsetvl elimination - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Add VLS modes VEC_PERM support[PR111311] [Committed,V2] RISC-V: Add VLS modes VEC_PERM support[PR111311] - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns [Committed] RISC-V: Add missing VLS mask bool mode reg -> reg patterns - - - -1- 2023-09-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm [V2] RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Expand fixed-vlmax/vls vector permutation in targethook RISC-V: Expand fixed-vlmax/vls vector permutation in targethook - - - -1- 2023-09-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix dump FILE of VSETVL PASS[PR111311] RISC-V: Fix dump FILE of VSETVL PASS[PR111311] - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add VLS modes VEC_PERM support[PR111311] RISC-V: Add VLS modes VEC_PERM support[PR111311] - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VLS floating-point operations predicate [Committed] RISC-V: Fix VLS floating-point operations predicate - - - -1- 2023-09-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Suppress bogus warning for VLS types RISC-V: Suppress bogus warning for VLS types - - - -1- 2023-09-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect nregs calculation for VLS modes RISC-V: Fix incorrect nregs calculation for VLS modes - - - -1- 2023-09-08 juzhe.zhong@rivai.ai Unresolved
RISC-V: Replace rtx REG for zero REGS operations RISC-V: Replace rtx REG for zero REGS operations - - - 1-- 2023-09-07 juzhe.zhong@rivai.ai Accepted
RISC-V: Add VLS mask modes mov patterns[PR111311] RISC-V: Add VLS mask modes mov patterns[PR111311] - - - -1- 2023-09-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable RVV scalable vectorization by default[PR111311] RISC-V: Enable RVV scalable vectorization by default[PR111311] - - - 1-- 2023-09-07 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] RISC-V: Remove incorrect earliest vsetvl post optimization[PR111313] - - - -1- 2023-09-07 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] [Committed,V2] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] - - - 1-- 2023-09-06 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295] RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295] - - - -1- 2023-09-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit - - - -1- 2023-09-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] - - - 1-- 2023-09-06 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Support Dynamic LMUL Cost model [V2] RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Export functions as global extern preparing for dynamic LMUL patch use RISC-V: Export functions as global extern preparing for dynamic LMUL patch use - - - -1- 2023-09-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support Dynamic LMUL Cost model RISC-V: Support Dynamic LMUL Cost model - - - -1- 2023-09-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix Dynamic LMUL compile option RISC-V: Fix Dynamic LMUL compile option - - - -1- 2023-09-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add dynamic LMUL compile option RISC-V: Add dynamic LMUL compile option - - - 1-- 2023-08-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Enable VECT_COMPARE_COSTS by default RISC-V: Enable VECT_COMPARE_COSTS by default - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add Vector cost model framework for RVV RISC-V: Add Vector cost model framework for RVV - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
[V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
test: Add xfail into slp-reduc-7.c for RVV VLA vectorization test: Add xfail into slp-reduc-7.c for RVV VLA vectorization - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
test: Adapt slp-26.c check for RVV test: Adapt slp-26.c check for RVV - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
test: Fix XPASS of RVV test: Fix XPASS of RVV - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
test: Add xfail for riscv_vector test: Add xfail for riscv_vector - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
[V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias middle-end: Apply MASK_LEN_LOAD_LANES/MASK_LEN_STORE_LANES to ivopts/alias - - - 1-- 2023-08-30 juzhe.zhong@rivai.ai Accepted
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