Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
« 1 2 3 4 … 12 13 »
Patch Series A/R/T S/W/F Date Submitter Delegate State
test: Fix bb-slp-33.c for RVV test: Fix bb-slp-33.c for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Fix FAIL of pr97428.c for RVV test: Fix FAIL of pr97428.c for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV# test: Fix FAIL of vect-sdiv-pow2-1.c for RVV test: Fix FAIL of vect-sdiv-pow2-1.c for RVV# - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Fix FAIL of SAD tests for RVV test: Fix FAIL of SAD tests for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
RISC-V regression test: Fix FAIL of bb-slp-39.c RISC-V regression test: Fix FAIL of bb-slp-39.c - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Fix FAIL of bb-slp-cond-1.c for RVV test: Fix FAIL of bb-slp-cond-1.c for RVV - - - 1-- 2023-11-06 juzhe.zhong@rivai.ai Accepted
test: Fix XPASS of bb-slp-43.c for RVV test: Fix XPASS of bb-slp-43.c for RVV - - - 1-- 2023-11-06 juzhe.zhong@rivai.ai Accepted
test: Fix XPASS of bb-slp-43.c for RVV test: Fix XPASS of bb-slp-43.c for RVV - - - 1-- 2023-11-06 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Early expand DImode vec_duplicate in RV32 system [V2] RISC-V: Early expand DImode vec_duplicate in RV32 system - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Early expand DImode vec_duplicate in RV32 system RISC-V: Early expand DImode vec_duplicate in RV32 system - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize [V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize [V2] VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization RISC-V: Enhance AVL propagation for complicate reduction auto-vectorization - - - -1- 2023-11-06 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix bug of vlds attribute [Committed] RISC-V: Fix bug of vlds attribute - - - -1- 2023-11-05 juzhe.zhong@rivai.ai Unresolved
OPTAB: Add mask_len_strided_load/mask_len_strided_store optab OPTAB: Add mask_len_strided_load/mask_len_strided_store optab - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
[tree-optimization/111721,V2] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask [tree-optimization/111721,V2] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] [Committed,V3] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of AVL propagation PASS RISC-V: Fix bug of AVL propagation PASS - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] [V2] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix redundant attributes [Committed] RISC-V: Fix redundant attributes - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
[tree-optimization/111721] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask [tree-optimization/111721] VECT: Support SLP for MASK_LEN_GATHER_LOAD with dummy mask - - - -1- 2023-11-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327] RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327] - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
[Commit,Pending,V2] RISC-V: Support strided load/store [Commit,Pending,V2] RISC-V: Support strided load/store - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
[Committed] NFC: Fix whitespace [Committed] NFC: Fix whitespace - - - -1- 2023-11-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support strided load/store RISC-V: Support strided load/store - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize VECT: Support mask_len_strided_load/mask_len_strided_store in loop vectorize - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
[V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN [V2] OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN - - - -1- 2023-10-31 juzhe.zhong@rivai.ai Unresolved
OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN OPTABS/IFN: Add mask_len_strided_load/mask_len_strided_store OPTABS/IFN - - - -1- 2023-10-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32 - - - -1- 2023-10-28 juzhe.zhong@rivai.ai Unresolved
[NFC] RISC-V: Move lmul calculation into macro [NFC] RISC-V: Move lmul calculation into macro - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask VECT: Support SLP MASK_LEN_GATHER_LOAD with conditional mask - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[V2] DOC: Update COND_LEN document [V2] DOC: Update COND_LEN document - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[Ready,to,commit,V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization [Ready,to,commit,V3] RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - 2 -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
DOC: Update COND_LEN document DOC: Update COND_LEN document - - - -1- 2023-10-26 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization [V2] RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Export some functions from riscv-vsetvl to riscv-v RISC-V: Export some functions from riscv-vsetvl to riscv-v - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Change MD attribute avl_type into avl_type_idx[NFC] RISC-V: Change MD attribute avl_type into avl_type_idx[NFC] - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite RISC-V: Fix multiple EXCESS test FAILs in RVV testsuite - - - -1- 2023-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add AVL propagation PASS for RVV auto-vectorization RISC-V: Add AVL propagation PASS for RVV auto-vectorization - - - -1- 2023-10-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] [Committed] RISC-V: Fix ICE of RTL CHECK on VSETVL PASS[PR111947] - - - -1- 2023-10-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] [V2] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] RISC-V: Fix ICE for the fusion case from vsetvl to scalar move[PR111927] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix typo[VSETVL PASS] [Committed] RISC-V: Fix typo[VSETVL PASS] - - - -1- 2023-10-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix AVL_TYPE attribute of tuple mode mov<mode> RISC-V: Fix AVL_TYPE attribute of tuple mode mov<mode> - - - 1-- 2023-10-22 juzhe.zhong@rivai.ai Accepted
RISC-V: Rename some variables of vector_block_info[NFC] RISC-V: Rename some variables of vector_block_info[NFC] - - - -1- 2023-10-20 juzhe.zhong@rivai.ai Unresolved
[V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V5] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction [V2] RISC-V: Fix failed hoist in LICM of vmv.v.x instruction - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix failed hoist in LICM of vmv.v.x instruction RISC-V: Fix failed hoist in LICM of vmv.v.x instruction - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx RISC-V: Optimize consecutive permutation index pattern by vrgather.vi/vx - - - -1- 2023-10-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832] RISC-V: Enable more tests for dynamic LMUL and bug fix[PR111832] - - - -1- 2023-10-17 juzhe.zhong@rivai.ai Unresolved
[V4] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V4] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-17 juzhe.zhong@rivai.ai Unresolved
[V4] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V4] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V3] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store [V2] RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. RISC-V: Use VLS modes if the NITERS is known and smaller than VLS mode elements. - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store RISC-V: Fix unexpected big LMUL choosing in dynamic LMUL model for non-adjacent load/store - - - -1- 2023-10-16 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix vsingle attribute [Committed] RISC-V: Fix vsingle attribute - - - -1- 2023-10-15 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant iterators. [Committed] RISC-V: Remove redundant iterators. - - - -1- 2023-10-14 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Fix FAIL of bb-slp-68.c for RVV RISC-V Regression: Fix FAIL of bb-slp-68.c for RVV - - - 1-- 2023-10-13 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV - - - 1-- 2023-10-13 juzhe.zhong@rivai.ai Accepted
[V3] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V3] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-13 juzhe.zhong@rivai.ai Unresolved
[V2] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] [V2] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-12 juzhe.zhong@rivai.ai Unresolved
VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] VECT: Enhance SLP of MASK_LEN_GATHER_LOAD[PR111721] - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Fix incorrect index(offset) of gather/scatter [V3] RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix incorrect index(offset) of gather/scatter [V2] RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect index(offset) of gather/scatter RISC-V: Fix incorrect index(offset) of gather/scatter - - - -1- 2023-10-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable full coverage vect tests RISC-V: Enable full coverage vect tests - - - 1-- 2023-10-11 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove XFAIL of ssa-dom-cse-2.c RISC-V: Remove XFAIL of ssa-dom-cse-2.c - - - 1-- 2023-10-11 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Make pattern match more accurate of vect-live-2.c RISC-V Regression: Make pattern match more accurate of vect-live-2.c - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Fix FAIL of vect-multitypes-16.c for RVV RISC-V Regression: Fix FAIL of vect-multitypes-16.c for RVV - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Fix FAIL of pr65947-8.c for RVV RISC-V Regression: Fix FAIL of pr65947-8.c for RVV - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] [Committed] RISC-V: Add VLS BOOL mode vcond_mask[PR111751] - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add testcase for SCCVN optimization[PR111751] [Committed] RISC-V: Add testcase for SCCVN optimization[PR111751] - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Fix FAIL of predcom-2.c RISC-V Regression: Fix FAIL of predcom-2.c - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Make match patterns more accurate RISC-V Regression: Make match patterns more accurate - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV - - - -1- 2023-10-10 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Fix dump check of bb-slp-68.c RISC-V Regression: Fix dump check of bb-slp-68.c - - - 1-- 2023-10-10 juzhe.zhong@rivai.ai Accepted
RISC-V: Add available vector size for RVV RISC-V: Add available vector size for RVV - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
TEST: Add vectorization check TEST: Add vectorization check - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV RISC-V Regression test: Fix FAIL of slp-reduc-4.c for RVV - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV RISC-V Regression test: Fix slp-perm-4.c FAIL for RVV - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression test: Adapt SLP tests like ARM SVE RISC-V Regression test: Adapt SLP tests like ARM SVE - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression test: Fix FAIL of slp-12a.c RISC-V Regression test: Fix FAIL of slp-12a.c - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression tests: Fix FAIL of pr97832* for RVV RISC-V Regression tests: Fix FAIL of pr97832* for RVV - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression test: Fix FAIL of pr45752.c for RVV RISC-V Regression test: Fix FAIL of pr45752.c for RVV - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for RVV RISC-V Regression test: Fix FAIL of fast-math-slp-38.c for RVV - - - 1-- 2023-10-09 juzhe.zhong@rivai.ai Accepted
[V2] RISC-V: Support movmisalign of RVV VLA modes [V2] RISC-V: Support movmisalign of RVV VLA modes - - - -1- 2023-10-09 juzhe.zhong@rivai.ai Unresolved
TEST: Fix XPASS of outer loop vectorization tests for RVV TEST: Fix XPASS of outer loop vectorization tests for RVV - - - 1-- 2023-10-08 juzhe.zhong@rivai.ai Accepted
TEST: Fix dump FAIL for RVV TEST: Fix dump FAIL for RVV - - - 1-- 2023-10-08 juzhe.zhong@rivai.ai Accepted
TEST: Fix dump FAIL of vect-multitypes-16.c for RVV TEST: Fix dump FAIL of vect-multitypes-16.c for RVV - - - 1-- 2023-10-08 juzhe.zhong@rivai.ai Accepted
TEST: Fix dump FAIL for RVV (RISCV-V vector) TEST: Fix dump FAIL for RVV (RISCV-V vector) - - - 1-- 2023-10-08 juzhe.zhong@rivai.ai Accepted
RISC-V: Support movmisalign of RVV VLA modes RISC-V: Support movmisalign of RVV VLA modes - - - -1- 2023-10-08 juzhe.zhong@rivai.ai Unresolved
[V2] TEST: Fix vect_cond_arith_* dump checks for RVV [V2] TEST: Fix vect_cond_arith_* dump checks for RVV - - - 1-- 2023-10-08 juzhe.zhong@rivai.ai Accepted
TEST: Fix vect_cond_arith_* dump checks for RVV TEST: Fix vect_cond_arith_* dump checks for RVV - - - 1-- 2023-10-07 juzhe.zhong@rivai.ai Accepted
TEST: Fix XPASS of TSVC testsuites for RVV TEST: Fix XPASS of TSVC testsuites for RVV - - - 1-- 2023-10-07 juzhe.zhong@rivai.ai Accepted
RISC-V: Enable more tests of "vect" for RVV RISC-V: Enable more tests of "vect" for RVV - - - -1- 2023-10-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove @ of vec_series RISC-V: Remove @ of vec_series - - - -1- 2023-10-04 juzhe.zhong@rivai.ai Unresolved
ifcvt: Fix comments ifcvt: Fix comments - - - 1-- 2023-09-27 juzhe.zhong@rivai.ai Accepted
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