Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[Committed] RISC-V: Tweak generic vector COST model [Committed] RISC-V: Tweak generic vector COST model - - - --1 2023-12-14 juzhe.zhong@rivai.ai Not Applicable
[Committed] RISC-V: Adjust test [Committed] RISC-V: Adjust test - - - -1- 2023-12-14 juzhe.zhong@rivai.ai Unresolved
Middle-end: Do not model address cost for SELECT_VL style vectorization Middle-end: Do not model address cost for SELECT_VL style vectorization - - - -1- 2023-12-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add failed SLP testcase [Committed] RISC-V: Add failed SLP testcase - - - 1-- 2023-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV builtin vectorization cost model RISC-V: Add RVV builtin vectorization cost model - - - -1- 2023-12-14 juzhe.zhong@rivai.ai Unresolved
Middle-end: Adjust decrement IV style partial vectorization COST model Middle-end: Adjust decrement IV style partial vectorization COST model - - - 1-- 2023-12-13 juzhe.zhong@rivai.ai Accepted
RISC-V: Postpone full available optimization [VSETVL PASS] RISC-V: Postpone full available optimization [VSETVL PASS] - - - -1- 2023-12-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Apply vla vs. vls mode heuristic vector COST model RISC-V: Apply vla vs. vls mode heuristic vector COST model - - - -1- 2023-12-12 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor Dynamic LMUL codes RISC-V: Refactor Dynamic LMUL codes - - - -1- 2023-12-12 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC] [Committed] RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC] - - - -1- 2023-12-12 juzhe.zhong@rivai.ai Unresolved
[COMMITTED,V2] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS [COMMITTED,V2] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS - - - 1-- 2023-12-11 juzhe.zhong@rivai.ai Accepted
RISC-V: Robostify shuffle index used by vrgather and fix regression RISC-V: Robostify shuffle index used by vrgather and fix regression - - - -1- 2023-12-11 juzhe.zhong@rivai.ai Unresolved
RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V VSETVL PASS - - - 1-- 2023-12-11 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Fix ICE in extract_single_source [Committed] RISC-V: Fix ICE in extract_single_source - - - 1-- 2023-12-11 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove poly selftest when --preference=fixed-vlmax RISC-V: Remove poly selftest when --preference=fixed-vlmax - - - 1-- 2023-12-11 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Fix VLS mode movmiaslign bug [Committed] RISC-V: Fix VLS mode movmiaslign bug - - - -1- 2023-12-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highest overlap for wv instructions RISC-V: Support highest overlap for wv instructions - - - -1- 2023-12-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant check of better_main_loop_than_p in COST model [Committed] RISC-V: Remove redundant check of better_main_loop_than_p in COST model - - - -1- 2023-12-08 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Support interleave vector with different step sequence [Committed,V2] RISC-V: Support interleave vector with different step sequence - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix AVL propagation ICE for vleff/vlsegff RISC-V: Fix AVL propagation ICE for vleff/vlsegff - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support interleave vector with different step sequence for VLA SLP RISC-V: Support interleave vector with different step sequence for VLA SLP - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support interleave vector with different step sequence for VLA SLP RISC-V: Support interleave vector with different step sequence for VLA SLP - - - -1- 2023-12-07 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix PR112888 ICE [Committed] RISC-V: Fix PR112888 ICE - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix VSETVL PASS bug [Committed,V2] RISC-V: Fix VSETVL PASS bug - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS bug RISC-V: Fix VSETVL PASS bug - - - -1- 2023-12-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR RISC-V: Block VLSmodes according to TARGET_MAX_LMUL and BITS_PER_RISCV_VECTOR - - - -1- 2023-12-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add blocker for gather/scatter auto-vectorization RISC-V: Add blocker for gather/scatter auto-vectorization - - - -1- 2023-12-05 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix overlap group incorrect overlap on v0 [Committed,V2] RISC-V: Fix overlap group incorrect overlap on v0 - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support highest-number regno overlap for widen ternary [V2] RISC-V: Support highest-number regno overlap for widen ternary - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highest-number regno overlap for widen ternary vx instructions RISC-V: Support highest-number regno overlap for widen ternary vx instructions - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove earlyclobber from widen reduction RISC-V: Remove earlyclobber from widen reduction - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix overlap group incorrect overlap on v0 RISC-V: Fix overlap group incorrect overlap on v0 - - - -1- 2023-12-04 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Robostify the W43, W86, W87 constraint enabled attribute [Committed] RISC-V: Robostify the W43, W86, W87 constraint enabled attribute - - - -1- 2023-12-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect combine of extended scalar pattern RISC-V: Fix incorrect combine of extended scalar pattern - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW - - - 1-- 2023-12-01 juzhe.zhong@rivai.ai Accepted
RISC-V: Support highpart register overlap for widen vx/vf instructions RISC-V: Support highpart register overlap for widen vx/vf instructions - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS regression RISC-V: Fix VSETVL PASS regression - - - -1- 2023-12-01 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Remove earlyclobber for wx/wf instructions. [V2] RISC-V: Remove earlyclobber for wx/wf instructions. - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove earlyclobber for wx/wf instructions. RISC-V: Remove earlyclobber for wx/wf instructions. - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support widening register overlap for vf4/vf8 RISC-V: Support widening register overlap for vf4/vf8 - - - 1-- 2023-11-30 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Support highpart overlap for floating-point widen instructions [Committed] RISC-V: Support highpart overlap for floating-point widen instructions - - - -1- 2023-11-30 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Rename vconstraint into group_overlap [Committed] RISC-V: Rename vconstraint into group_overlap - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart overlap for vext.vf RISC-V: Support highpart overlap for vext.vf - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support highpart register overlap for vwcvt RISC-V: Support highpart register overlap for vwcvt - - - -1- 2023-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization RISC-V: Disallow poly (1,1) VLA SLP interleave vectorization - - - -1- 2023-11-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL PASS regression RISC-V: Fix VSETVL PASS regression - - - -1- 2023-11-27 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Disable AVL propagation of slidedown instructions [Committed] RISC-V: Disable AVL propagation of slidedown instructions - - - -1- 2023-11-26 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix typo [Committed] RISC-V: Fix typo - - - -1- 2023-11-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p RISC-V: Remove incorrect function gate gather_scatter_valid_offset_mode_p - - - -1- 2023-11-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix inconsistency among all vectorization hooks RISC-V: Fix inconsistency among all vectorization hooks - - - -1- 2023-11-24 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 [Committed] RISC-V: Disable BSWAP optimization for NUNITS < 4 - - - -1- 2023-11-24 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize a special case of VLA SLP [V2] RISC-V: Optimize a special case of VLA SLP - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize a special case of VLA SLP RISC-V: Optimize a special case of VLA SLP - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add wrapper for emit vec_extract[NFC] [Committed] RISC-V: Add wrapper for emit vec_extract[NFC] - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Disable AVL propagation of vrgather instruction [Committed,V2] RISC-V: Disable AVL propagation of vrgather instruction - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disable AVL propagation of vrgather instruction RISC-V: Disable AVL propagation of vrgather instruction - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Refine some codes of riscv-v.cc[NFC] [Committed] RISC-V: Refine some codes of riscv-v.cc[NFC] - - - -1- 2023-11-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect use of vcompress in permutation auto-vectorization RISC-V: Fix incorrect use of vcompress in permutation auto-vectorization - - - -1- 2023-11-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix permutation indice mode bug RISC-V: Fix permutation indice mode bug - - - -1- 2023-11-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add missing dump check of pr112438.c [Committed] RISC-V: Add missing dump check of pr112438.c - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[BUG,FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32 [BUG,FIX] RISC-V: Disallow COSNT_VECTOR for DI on RV32 - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix reduc_run-9.c test value check bug [Committed] RISC-V: Fix reduc_run-9.c test value check bug - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 [BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
RISC-V Regression: Remove scalable compile option RISC-V Regression: Remove scalable compile option - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
回复: Re: [PATCH] DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN 回复: Re: [PATCH] DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN - - - --1 2023-11-20 juzhe.zhong@rivai.ai Not Applicable
[BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute [BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Optimize constant AVL for LRA pattern [Committed,V2] RISC-V: Optimize constant AVL for LRA pattern - - - -1- 2023-11-19 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Fix bug of tuple move splitter [Committed,V3] RISC-V: Fix bug of tuple move splitter - - - 1-- 2023-11-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Refactor RVV iterators[NFC] RISC-V: Refactor RVV iterators[NFC] - - - -1- 2023-11-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix bug of tuple move splitter [V2] RISC-V: Fix bug of tuple move splitter - - - 1-- 2023-11-17 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix bug of tuple move splitter[PR112561] RISC-V: Fix bug of tuple move splitter[PR112561] - - - -1- 2023-11-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice RISC-V: Optimize VLA SLP with duplicate VLA shuffle indice - - - -1- 2023-11-17 juzhe.zhong@rivai.ai Unresolved
VECT: Clear LOOP_VINFO_USING_SELECT_VL_P when loop is not partial vectorized VECT: Clear LOOP_VINFO_USING_SELECT_VL_P when loop is not partial vectorized - - - 1-- 2023-11-16 juzhe.zhong@rivai.ai Accepted
RISC-V: Disallow RVV mode address for any load/store[PR112535] RISC-V: Disallow RVV mode address for any load/store[PR112535] - - - 1-- 2023-11-15 juzhe.zhong@rivai.ai Accepted
RISC-V: Support trailing vec_init optimization RISC-V: Support trailing vec_init optimization - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into loop vectorizer VECT: Add MASK_LEN_STRIDED_LOAD/MASK_LEN_STRIDED_STORE into loop vectorizer - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN DOC/IFN/OPTAB: Add mask_len_strided_load/mask_len_strided_store DOC/OPTAB/IFN - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Commit,QUEUE,V3] RISC-V: Support strided load/store [Commit,QUEUE,V3] RISC-V: Support strided load/store - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix init-2.c assembly check [Committed] RISC-V: Fix init-2.c assembly check - - - -1- 2023-11-14 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Adapt VLS init tests [Committed] RISC-V: Adapt VLS init tests - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Optimize combine sequence by merge approach [Committed,V3] RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Optimize combine sequence by merge approach [V2] RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize combine sequence by merge approach RISC-V: Optimize combine sequence by merge approach - - - -1- 2023-11-13 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add test for PR112469 [Committed] RISC-V: Add test for PR112469 - - - 1-- 2023-11-10 juzhe.zhong@rivai.ai Accepted
[V2] Middle-end: Fix bug of induction variable vectorization for RVV [V2] Middle-end: Fix bug of induction variable vectorization for RVV - - - 1-- 2023-11-10 juzhe.zhong@rivai.ai Accepted
RISC-V: Add combine optimization by slideup for vec_init vectorization RISC-V: Add combine optimization by slideup for vec_init vectorization - - - -1- 2023-11-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Robustify vec_init pattern[NFC] RISC-V: Robustify vec_init pattern[NFC] - - - -1- 2023-11-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Move cond_copysign from combine pattern to autovec pattern RISC-V: Move cond_copysign from combine pattern to autovec pattern - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add PR112450 test to avoid regression [Committed] RISC-V: Add PR112450 test to avoid regression - - - 1-- 2023-11-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix dynamic LMUL cost model ICE RISC-V: Fix dynamic LMUL cost model ICE - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix dynamic tests [NFC] [Committed] RISC-V: Fix dynamic tests [NFC] - - - -1- 2023-11-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix VSETVL VL check condition bug [Committed] RISC-V: Fix VSETVL VL check condition bug - - - -1- 2023-11-08 juzhe.zhong@rivai.ai Unresolved
Middle-end: Fix bug of induction variable vectorization for RVV Middle-end: Fix bug of induction variable vectorization for RVV - - - 1-- 2023-11-08 juzhe.zhong@rivai.ai Accepted
RISC-V: Normalize user vsetvl intrinsics[PR112092] RISC-V: Normalize user vsetvl intrinsics[PR112092] - - - -1- 2023-11-08 juzhe.zhong@rivai.ai Unresolved
[V3] test: Fix FAIL of pr97428.c for RVV [V3] test: Fix FAIL of pr97428.c for RVV - - - -1- 2023-11-07 juzhe.zhong@rivai.ai Unresolved
[V2] test: Fix bb-slp-33.c for RVV [V2] test: Fix bb-slp-33.c for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Recover sdiv_pow2 check and remove test of RISC-V test: Recover sdiv_pow2 check and remove test of RISC-V - - - -1- 2023-11-07 juzhe.zhong@rivai.ai Unresolved
[V2] test: Fix FAIL of pr97428.c for RVV [V2] test: Fix FAIL of pr97428.c for RVV - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RISC-V into vect_cmdline_needed RISC-V: Add RISC-V into vect_cmdline_needed - - - 1-- 2023-11-07 juzhe.zhong@rivai.ai Accepted
test: Fix FAIL of pr65518.c for RVV[PR112420] test: Fix FAIL of pr65518.c for RVV[PR112420] - - - --1 2023-11-07 juzhe.zhong@rivai.ai Not Applicable
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