Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Fix ICE of visiting non-existing block in CFG. RISC-V: Fix ICE of visiting non-existing block in CFG. - - - 1-- 2022-12-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. RISC-V: Fix ICE for avl_info deprecated copy and pp_print error. - - - 1-- 2022-12-23 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix vle constraints RISC-V: Fix vle constraints - - - 1-- 2022-12-23 juzhe.zhong@rivai.ai Accepted
RISC-V: Support vle.v/vse.v intrinsics RISC-V: Support vle.v/vse.v intrinsics - - - -1- 2022-12-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name. - - - 1-- 2022-12-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove side effects of vsetvl pattern in RTL. RISC-V: Remove side effects of vsetvl pattern in RTL. - - - 1-- 2022-12-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs in properties - - - 1-- 2022-12-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix incorrect annotation RISC-V: Fix incorrect annotation - - - 1-- 2022-12-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix muti-line condition format RISC-V: Fix muti-line condition format - - - 1-- 2022-12-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Simplify ASM checks 2 RISC-V: Simplify ASM checks 2 - - - -1- 2022-12-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Simplify ASM checks. RISC-V: Simplify ASM checks. - - - -1- 2022-12-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unit-stride store from ta attribute RISC-V: Remove unit-stride store from ta attribute - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove unused redundant vector attributes RISC-V: Remove unused redundant vector attributes - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix annotation RISC-V: Fix annotation - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add testcases for VSETVL PASS 5 RISC-V: Add testcases for VSETVL PASS 5 - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for VSETVL PASS 4 RISC-V: Add testcases for VSETVL PASS 4 - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for VSETVL PASS 3 RISC-V: Add testcases for VSETVL PASS 3 - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for VSETVL PASS 2 RISC-V: Add testcases for VSETVL PASS 2 - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for VSETVL PASS RISC-V: Add testcases for VSETVL PASS - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support VSETVL PASS for RVV support RISC-V: Support VSETVL PASS for RVV support - - - -1- 2022-12-14 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix RVV machine mode attribute configuration RISC-V: Fix RVV machine mode attribute configuration - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Change vlmul printing rule RISC-V: Change vlmul printing rule - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix RVV mask mode size RISC-V: Fix RVV mask mode size - - - 1-- 2022-12-14 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - -1- 2022-11-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst - - - 1-- 2022-11-28 juzhe.zhong@rivai.ai Accepted
RISC-V: Add attributes for VSETVL PASS RISC-V: Add attributes for VSETVL PASS - - - -1- 2022-11-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add duplicate vector support. RISC-V: Add duplicate vector support. - - - 1-- 2022-11-25 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV registers register spilling RISC-V: Add RVV registers register spilling - - - -1- 2022-11-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix RVV testcases. RISC-V: Fix RVV testcases. - - - 1-- 2022-10-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Change constexpr back to CONSTEXPR RISC-V: Change constexpr back to CONSTEXPR - - - 1-- 2022-10-27 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix a mistake in previous patch. RISC-V: Fix a mistake in previous patch. - - - 1-- 2022-10-25 juzhe.zhong@rivai.ai Accepted
RISC-V: ADJUST_NUNITS according to -march. RISC-V: ADJUST_NUNITS according to -march. - - - -1- 2022-10-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix typo. RISC-V: Fix typo. - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Support (set (mem) (const_poly_int)) RISC-V: Support (set (mem) (const_poly_int)) - - - -1- 2022-10-24 juzhe.zhong@rivai.ai Unresolved
RISC-V: Replace CONSTEXPR with constexpr RISC-V: Replace CONSTEXPR with constexpr - - - -1- 2022-10-24 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Support load/store in mov<mode> pattern for RVV modes. RISC-V: Support load/store in mov<mode> pattern for RVV modes. - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove unused TI/TF vector modes. RISC-V: Remove unused TI/TF vector modes. - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Support (set (mem) (const_poly_int)) RISC-V: Support (set (mem) (const_poly_int)) - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF. RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF. - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix REG_CLASS_CONTENTS. RISC-V: Fix REG_CLASS_CONTENTS. - - - 1-- 2022-10-24 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. - - - -1- 2022-10-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add RVV intrinsic basic framework. RISC-V: Add RVV intrinsic basic framework. - - - 1-- 2022-10-17 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix format[NFC] RISC-V: Fix format[NFC] - - - -1- 2022-10-17 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Reorganize mangle_builtin_type.[NFC] RISC-V: Reorganize mangle_builtin_type.[NFC] - - - 1-- 2022-10-14 juzhe.zhong@rivai.ai Accepted
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