Show patches with: Submitter = juzhe.zhong@rivai.ai       |    Archived = No       |   1246 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add vsll.vx C++ API tests RISC-V: Add vsll.vx C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsra.vx C API tests RISC-V: Add vsra.vx C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsrl.vx C API tests RISC-V: Add vsrl.vx C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add RVV shift.vx C/C++ API support RISC-V: Add RVV shift.vx C/C++ API support - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vdiv*.vv C++ API tests RISC-V: Add vdiv*.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vmax*.vv C++ API tests RISC-V: Add vmax*.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vmin*.vv C++ API tests RISC-V: Add vmin*.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vor.vv C++ API tests RISC-V: Add vor.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vrem*.vv C++ API tests RISC-V: Add vrem*.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsll.vv C++ API tests RISC-V: Add vsll.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsra.vv C++ API tests RISC-V: Add vsra.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsrl.vv C++ API tests RISC-V: Add vsrl.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vand.vv C++ API tests RISC-V: Add vand.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vxor.vv C++ API tests RISC-V: Add vxor.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vadd.vv C++ API tests RISC-V: Add vadd.vv C++ API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add binop constraint tests RISC-V: Add binop constraint tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vadd.vv C API tests RISC-V: Add vadd.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vand.vv C API tests RISC-V: Add vand.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vdiv*.vv C API tests RISC-V: Add vdiv*.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vmax*.vv C API tests RISC-V: Add vmax*.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vmin*.vv C API tests RISC-V: Add vmin*.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vor.vv C API tests RISC-V: Add vor.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vrem*.vv C API tests RISC-V: Add vrem*.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsll.vv C API tests RISC-V: Add vsll.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsra.vv C API tests RISC-V: Add vsra.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add srl.vv C API tests RISC-V: Add srl.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsub.vv C API tests RISC-V: Add vsub.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vxor.vv C API tests RISC-V: Add vxor.vv C API tests - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add integer binary vv C/C++ API support RISC-V: Add integer binary vv C/C++ API support - - - 1-- 2023-01-31 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei64 C++ API intrinsic testcase RISC-V: Add vloxei64 C++ API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei32 C++ API intrinsic testcases RISC-V: Add vloxei32 C++ API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei16 C++ API intrinsic testcases RISC-V: Add vloxei16 C++ API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei8 C++ API intrinsic testcase RISC-V: Add vloxei8 C++ API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei64 C++ API intrinsic testcases RISC-V: Add vluxei64 C++ API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei32 C++ intrinsic API testcase RISC-V: Add vluxei32 C++ intrinsic API testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei16 C++ API intrinsic testcases RISC-V: Add vluxei16 C++ API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei8 C++ API intrinsic testcase RISC-V: Add vluxei8 C++ API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsuxei* C++ API intrinsics testcases RISC-V: Add vsuxei* C++ API intrinsics testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsuxei C API intrinsic testcase RISC-V: Add vsuxei C API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsoxei C API intrinsic testcase RISC-V: Add vsoxei C API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsoxei32 && vsoxei64 C++ API intrinsic testcase RISC-V: Add vsoxei32 && vsoxei64 C++ API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vsoxei8 && vsoxei16 C++ API intrinsic testcase RISC-V: Add vsoxei8 && vsoxei16 C++ API intrinsic testcase - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei64 C API intrinsic testcases RISC-V: Add vluxei64 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei32 C API intrinsic testcases RISC-V: Add vluxei32 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei16 C API intrinsic testcases RISC-V: Add vluxei16 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vluxei8 C API intrinsic testcases RISC-V: Add vluxei8 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei64 C API intrinsic testcases RISC-V: Add vloxei64 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei32 C API intrinsic testcases RISC-V: Add vloxei32 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei16 C API intrinsic testcases RISC-V: Add vloxei16 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vloxei8 C API intrinsic testcases RISC-V: Add vloxei8 C API intrinsic testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add indexed loads/stores constraints testcases RISC-V: Add indexed loads/stores constraints testcases - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add VSETVL testcases for indexed loads/stores. RISC-V: Add VSETVL testcases for indexed loads/stores. - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add indexed loads/stores C/C++ intrinsic support RISC-V: Add indexed loads/stores C/C++ intrinsic support - - - 1-- 2023-01-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vlse/vsse C/C++ intrinsic testcases RISC-V: Add vlse/vsse C/C++ intrinsic testcases - - - 1-- 2023-01-27 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vlse/vsse intrinsics support RISC-V: Add vlse/vsse intrinsics support - - - 1-- 2023-01-27 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove redundant attributes RISC-V: Remove redundant attributes - - - 1-- 2023-01-27 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix testcases check. RISC-V: Fix testcases check. - - - -1- 2023-01-27 juzhe.zhong@rivai.ai Repeat Merge
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes - - - 1-- 2023-01-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vlse/vsse C/C++ intrinsics testcases RISC-V: Add vlse/vsse C/C++ intrinsics testcases - - - 1-- 2023-01-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vlse/vsse C/C++ API intrinsics support RISC-V: Add vlse/vsse C/C++ API intrinsics support - - - -1- 2023-01-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vle/vse C++ overloaded API intrinsic testcases RISC-V: Add vle/vse C++ overloaded API intrinsic testcases - - - 1-- 2023-01-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix vop_m overloaded C++ API name. RISC-V: Fix vop_m overloaded C++ API name. - - - 1-- 2023-01-20 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vse.v C API intrinsics testcases RISC-V: Add vse.v C API intrinsics testcases - - - 1-- 2023-01-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Add vle.v C API intrinsics testcases RISC-V: Add vle.v C API intrinsics testcases - - - 1-- 2023-01-19 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix pred_mov constraint for vle.v RISC-V: Fix pred_mov constraint for vle.v - - - -1- 2023-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add vlm/vsm C/C++ API intrinsics support RISC-V: Add vlm/vsm C/C++ API intrinsics support - - - -1- 2023-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Finalize testcases for final version VSETVL PASS. RISC-V: Finalize testcases for final version VSETVL PASS. - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Finalize VSETVL PASS implementation RISC-V: Finalize VSETVL PASS implementation - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add :: for static function calling to avoid confusing RISC-V: Add :: for static function calling to avoid confusing - - - 1-- 2023-01-18 juzhe.zhong@rivai.ai Accepted
RISC-V: Refine function args of some functions. RISC-V: Refine function args of some functions. - - - 1-- 2023-01-18 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix bug of before_p function RISC-V: Fix bug of before_p function - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Change parse_insn into public for future use. RISC-V: Change parse_insn into public for future use. - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Reorder VSETVL PASS location RISC-V: Reorder VSETVL PASS location - - - 1-- 2023-01-18 juzhe.zhong@rivai.ai Accepted
RISC-V: Clang-format some annotations[NFC] RISC-V: Clang-format some annotations[NFC] - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove DCE in VSETVL PASS RISC-V: Remove DCE in VSETVL PASS - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Change VSETVL PASS always call split_all_insns RISC-V: Change VSETVL PASS always call split_all_insns - - - 1-- 2023-01-18 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix incorrect attributes of vsetvl instructions pattern RISC-V: Fix incorrect attributes of vsetvl instructions pattern - - - -1- 2023-01-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add the rest testcases of AVL=REG support RISC-V: Add the rest testcases of AVL=REG support - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for AVL=REG support RISC-V: Add testcases for AVL=REG support - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Adjust testcases for AVL=REG support RISC-V: Adjust testcases for AVL=REG support - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Call DCE to remove redundant instructions created by the PASS RISC-V: Call DCE to remove redundant instructions created by the PASS - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Add probability model of each block to prevent endless loop of Phase 3 RISC-V: Add probability model of each block to prevent endless loop of Phase 3 - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove dirty_pat since it is redundant RISC-V: Remove dirty_pat since it is redundant - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Rename insn into rinsn for rtx_insn * RISC-V: Rename insn into rinsn for rtx_insn * - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Avoid redundant flow in backward fusion RISC-V: Avoid redundant flow in backward fusion - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refine codes in backward fusion RISC-V: Refine codes in backward fusion - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Avoid redundant flow in forward fusion RISC-V: Avoid redundant flow in forward fusion - - - -1- 2023-01-09 juzhe.zhong@rivai.ai Unresolved
RISC-V: Cleanup the codes of bitmap create and free [NFC] RISC-V: Cleanup the codes of bitmap create and free [NFC] - - - 1-- 2023-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Add testcases for IMM (0 ~ 31) AVL RISC-V: Add testcases for IMM (0 ~ 31) AVL - - - 1-- 2023-01-04 juzhe.zhong@rivai.ai Accepted
RISC-V: Refine Phase 3 of VSETVL PASS RISC-V: Refine Phase 3 of VSETVL PASS - - - 1-- 2023-01-04 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix bugs of available condition. RISC-V: Fix bugs of available condition. - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Simplify codes of changing vsetvl instruction RISC-V: Simplify codes of changing vsetvl instruction - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix backward_propagate_worthwhile_p RISC-V: Fix backward_propagate_worthwhile_p - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix wrong in_group flag in validate_change call function RISC-V: Fix wrong in_group flag in validate_change call function - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix vsetivli instruction asm for IMM AVL RISC-V: Fix vsetivli instruction asm for IMM AVL - - - 1-- 2023-01-03 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix inferior codegen for vse intrinsics. RISC-V: Fix inferior codegen for vse intrinsics. - - - 1-- 2022-12-29 juzhe.zhong@rivai.ai Accepted
RISC-V: Change form of iterating blocks RISC-V: Change form of iterating blocks - - - 1-- 2022-12-28 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix pointer tree type for store pointer. RISC-V: Fix pointer tree type for store pointer. - - - 1-- 2022-12-28 juzhe.zhong@rivai.ai Accepted
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