Show patches with: Submitter = Jiawei       |    State = Action Required       |   5 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add XiangShan Nanhu microarchitecture. RISC-V: Add XiangShan Nanhu microarchitecture. - - - -1- 2024-02-27 Jiawei Unresolved
[v2] RISC-V: Supports RISC-V Profiles in '-march' option. [v2] RISC-V: Supports RISC-V Profiles in '-march' option. - - - -1- 2023-12-12 Jiawei Unresolved
[RFC] RISC-V: Support RISC-V Profiles in -march option. [RFC] RISC-V: Support RISC-V Profiles in -march option. - - - -1- 2023-11-20 Jiawei Unresolved
RISC-V:Add '-m[no]-csr-check' option in gcc. RISC-V:Add '-m[no]-csr-check' option in gcc. - - - --- 2022-09-08 Jiawei New
testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works - - - --- 2022-07-28 Jiawei New