Show patches with: Submitter = Li Xu       |    State = Action Required       |   33 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2] RISC-V: Add riscv_vector_cc function attribute [v2] RISC-V: Add riscv_vector_cc function attribute - - - -1- 2024-03-01 Li Xu Unresolved
RISC-V: Add riscv_vector_cc function attribute RISC-V: Add riscv_vector_cc function attribute - - - -1- 2024-02-27 Li Xu Unresolved
[v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420] [v2] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420] - - - -1- 2024-01-22 Li Xu Unresolved
RISC-V: Bugfix for resolve_overloaded_builtin[PR113420] RISC-V: Bugfix for resolve_overloaded_builtin[PR113420] - - - -1- 2024-01-19 Li Xu Unresolved
testsuite: Fix dump checks under different riscv-sim for RVV. testsuite: Fix dump checks under different riscv-sim for RVV. - - - -1- 2023-12-19 Li Xu Unresolved
testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV. testsuite: Fix cpymem-2.c dump checks under different riscv-sim for RVV. - - - -1- 2023-12-19 Li Xu Unresolved
[v2] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV. [v2] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV. - - - -1- 2023-12-18 Li Xu Unresolved
testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV. testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV. - - - -1- 2023-12-18 Li Xu Unresolved
RISC-V: Remove useless modes RISC-V: Remove useless modes - - - -1- 2023-12-06 Li Xu Unresolved
RISC-V: Add explicit braces to eliminate warning. RISC-V: Add explicit braces to eliminate warning. - - - -1- 2023-11-29 Li Xu Unresolved
RISC-V: Implement -mmemcpy-strategy= options[PR112537] RISC-V: Implement -mmemcpy-strategy= options[PR112537] - - - -1- 2023-11-17 Li Xu Unresolved
RISC-V: Support vcreate intrinsics for non-tuple types RISC-V: Support vcreate intrinsics for non-tuple types - - - -1- 2023-11-02 Li Xu Unresolved
RISC-V: Support vundefine intrinsics for tuple types RISC-V: Support vundefine intrinsics for tuple types - - - -1- 2023-11-01 Li Xu Unresolved
[v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic [v6] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic - - - -1- 2023-10-31 Li Xu Unresolved
RISC-V: Fix scan-assembler-times of RVV test case RISC-V: Fix scan-assembler-times of RVV test case - - - -1- 2023-10-07 Li Xu Unresolved
[v2] RISC-V: Bugfix for RTL check[PR111533] [v2] RISC-V: Bugfix for RTL check[PR111533] - - - -1- 2023-09-28 Li Xu Unresolved
RISC-V: Bugfix for RTL check[PR111533] RISC-V: Bugfix for RTL check[PR111533] - - - -1- 2023-09-27 Li Xu Unresolved
[V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] [V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - -1- 2023-09-22 Li Xu Unresolved
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - -1- 2023-09-22 Li Xu Unresolved
RISC-V: Optimized for strided load/store with stride == element width[PR111450] RISC-V: Optimized for strided load/store with stride == element width[PR111450] - - - -1- 2023-09-21 Li Xu Unresolved
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] - - - -1- 2023-09-18 Li Xu Unresolved
[v3] RISC-V: Elimilate warning in class vcreate [v3] RISC-V: Elimilate warning in class vcreate - - - -1- 2023-09-12 Li Xu Unresolved
[v2] RISC-V: Elimilate warning in class vcreate [v2] RISC-V: Elimilate warning in class vcreate - - - -1- 2023-09-12 Li Xu Unresolved
RISC-V: Elimilate warning RISC-V: Elimilate warning - - - -1- 2023-09-12 Li Xu Unresolved
RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u] RISC-V: Remove vxrm parameter for vsadd[u] and vssub[u] - - - -1- 2023-07-28 Li Xu Unresolved
RISC-V: Fix vector tuple intrinsic RISC-V: Fix vector tuple intrinsic - - - -1- 2023-07-26 Li Xu Unresolved
[v2] RISC-V: Fix vector tuple intrinsic [v2] RISC-V: Fix vector tuple intrinsic - - - -1- 2023-07-26 Li Xu Unresolved
RISC-V: Fix vector tuple intrinsic RISC-V: Fix vector tuple intrinsic - - - -1- 2023-07-26 Li Xu Unresolved
[v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic [v2] RISC-V: fix expand function of vlmul_ext RVV intrinsic - - - -1- 2023-06-25 Li Xu Unresolved
RISC-V: force arg and target to reg rtx under -O0 RISC-V: force arg and target to reg rtx under -O0 - - - -1- 2023-06-25 Li Xu Unresolved
[v2] RISC-V: Fix VWEXTF iterator requirement [v2] RISC-V: Fix VWEXTF iterator requirement - - - -1- 2023-06-19 Li Xu Unresolved
RISC-V: Fix iterator requirement RISC-V: Fix iterator requirement - - - -1- 2023-06-19 Li Xu Unresolved
RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. - - - -1- 2023-06-05 Li Xu Unresolved