Show patches with: Submitter = Vineet Gupta       |    State = Action Required       |   21 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-17 Vineet Gupta Unresolved
[COMITTED,2/2] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] [COMITTED,1/2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-17 Vineet Gupta Unresolved
RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] RISC-V: fix some vsetvl debug info in pass's Phase 2 code [NFC] - - - -1- 2024-01-16 Vineet Gupta Unresolved
[v2] RISC-V: RVV: add toggle to control vsetvl pass behavior [v2] RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2024-01-16 Vineet Gupta Unresolved
RISC-V: RVV: add toggle to control vsetvl pass behavior RISC-V: RVV: add toggle to control vsetvl pass behavior - - - -1- 2023-12-22 Vineet Gupta Unresolved
[Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] [Committed] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - - - -1- 2023-11-15 Vineet Gupta Unresolved
RISC-V: fix vsetvli pass testsuite failure [PR/112447] RISC-V: fix vsetvli pass testsuite failure [PR/112447] - - - -1- 2023-11-15 Vineet Gupta Unresolved
[COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output [COMMITTED] RISC-V/testsuite/pr111466.c: update test and expected output - - - -1- 2023-10-17 Vineet Gupta Unresolved
[v2] RISC-V/testsuite/pr111466.c: update test and expected output [v2] RISC-V/testsuite/pr111466.c: update test and expected output - - - -1- 2023-10-17 Vineet Gupta Unresolved
RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W RISC-V/testsuite/pr111466.c: fix expected output to not detect SEXT.W - - - -1- 2023-10-17 Vineet Gupta Unresolved
[Committed] RISC-V: zicond: Fix opt2 pattern [Committed] RISC-V: zicond: Fix opt2 pattern - - - -1- 2023-09-05 Vineet Gupta Unresolved
[v2] RISC-V: zicond: Fix opt2 pattern [v2] RISC-V: zicond: Fix opt2 pattern - - - -1- 2023-09-01 Vineet Gupta Unresolved
RISC-V: zicond: remove bogus opt2 pattern RISC-V: zicond: remove bogus opt2 pattern - - - -1- 2023-08-30 Vineet Gupta Unresolved
[3/3] testsuite: print any leaking torture options for debugging Unbork testsuite for multlib setups - - - -1- 2023-05-31 Vineet Gupta Unresolved
[2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp Unbork testsuite for multlib setups - - - -1- 2023-05-31 Vineet Gupta Unresolved
RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] - 1 - -1- 2023-03-01 Vineet Gupta Repeat Merge
RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understand - - - --- 2022-09-02 Vineet Gupta New
[v3] RISC-V: remove deprecate pic code model macro [v3] RISC-V: remove deprecate pic code model macro - - - --- 2022-09-02 Vineet Gupta New
[v2] RISC-V: remove deprecate pic code model macro [v2] RISC-V: remove deprecate pic code model macro - - - --- 2022-09-02 Vineet Gupta New
[2/2] RISC-V: remove CM_PIC as it doesn't do much PIC cleanup - - - --- 2022-08-30 Vineet Gupta New
[1/2] RISC-V: remove deprecate pic code model macro PIC cleanup - - - --- 2022-08-30 Vineet Gupta New