Show patches with: Submitter = jeevitha       |   17 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950] [V3] rs6000: Don't ICE when compiling the __builtin_vsx_splat_2di built-in [PR113950] - - - 1-- 2024-03-03 jeevitha Accepted
[V2] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950] [V2] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950] - - - 1-- 2024-02-26 jeevitha Accepted
rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950] rs6000: Don't allow immediate value in the vsx_splat pattern [PR113950] - - - 1-- 2024-02-26 jeevitha Accepted
rs6000: load high and low part of 128bit vector independently [PR110040] rs6000: load high and low part of 128bit vector independently [PR110040] - - - 1-- 2024-02-26 jeevitha Accepted
rs6000: Fix issue in specifying PTImode as an attribute [PR106895] rs6000: Fix issue in specifying PTImode as an attribute [PR106895] - - - 1-- 2024-02-23 jeevitha Accepted
[v2] rs6000: Change bitwise xor to an equality operator [PR106907] [v2] rs6000: Change bitwise xor to an equality operator [PR106907] - - - 1-- 2023-10-11 jeevitha Accepted
rs6000: Disable PCREL for unsupported targets [PR111045] rs6000: Disable PCREL for unsupported targets [PR111045] - - - 1-- 2023-08-21 jeevitha Accepted
rs6000: Fix issue in specifying PTImode as an attribute [PR106895] rs6000: Fix issue in specifying PTImode as an attribute [PR106895] - - - 1-- 2023-07-20 jeevitha Accepted
[V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411] [V2] rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411] - - - -1- 2023-07-19 jeevitha Unresolved
[V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110… [V2] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110… - - - 1-- 2023-07-17 jeevitha Accepted
rs6000: Don't ICE when generating vector pair load/store insns [PR110411] rs6000: Don't ICE when generating vector pair load/store insns [PR110411] - - - 1-- 2023-07-05 jeevitha Accepted
rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] rs6000: Change GPR2 to volatile & non-fixed register for function that does not use TOC [PR110320] - - - 1-- 2023-06-23 jeevitha Accepted
rs6000: Change bitwise xor to inequality operator [PR106907] rs6000: Change bitwise xor to inequality operator [PR106907] - - - 1-- 2023-06-12 jeevitha Accepted
Add parentheses to clarify precedence between operators [PR106907] Add parentheses to clarify precedence between operators [PR106907] - - - 1-- 2023-06-07 jeevitha Accepted
rs6000: Remove redundant initialization [PR106907] rs6000: Remove redundant initialization [PR106907] - - - 1-- 2023-06-07 jeevitha Accepted
rs6000: Remove duplicate expression [PR106907] rs6000: Remove duplicate expression [PR106907] - - - 1-- 2023-06-05 jeevitha Accepted
MAINTAINERS: Add myself to write after approval MAINTAINERS: Add myself to write after approval - - - 1-- 2023-05-31 jeevitha Accepted