Show patches with: Submitter = juzhe.zhong@rivai.ai       |   1279 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: add option -m(no-)autovec-segment RISC-V: add option -m(no-)autovec-segment - - - -1- 2024-02-26 juzhe.zhong@rivai.ai Corrupt patch
RISC-V: Fix infinite compilation of VSETVL PASS RISC-V: Fix infinite compilation of VSETVL PASS - - - -1- 2024-02-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Expand VLMAX scalar move in reduction RISC-V: Expand VLMAX scalar move in reduction - - - -1- 2024-02-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow LICM hoist POLY_INT configuration code sequence RISC-V: Allow LICM hoist POLY_INT configuration code sequence - - - 1-- 2024-02-01 juzhe.zhong@rivai.ai Accepted
RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS - - - -1- 2024-02-01 juzhe.zhong@rivai.ai Unresolved
[v2] RISC-V: Suppress the vsetvl fusion for conflict successors [v2] RISC-V: Suppress the vsetvl fusion for conflict successors - - - -1- 2024-02-01 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disable the vsetvl fusion for conflict successors RISC-V: Disable the vsetvl fusion for conflict successors - - - -1- 2024-02-01 juzhe.zhong@rivai.ai Unresolved
middle-end: Enhance conditional reduction vectorization by re-association in ifcvt [PR109088] middle-end: Enhance conditional reduction vectorization by re-association in ifcvt [PR109088] - - - 1-- 2024-01-30 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Fix regression [Committed] RISC-V: Fix regression - - - -1- 2024-01-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETLV PASS compile-time issue RISC-V: Fix VSETLV PASS compile-time issue - - - -1- 2024-01-29 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Refine some codes of VSETVL PASS [NFC] [Committed] RISC-V: Refine some codes of VSETVL PASS [NFC] - - - -1- 2024-01-26 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix incorrect LCM delete bug [VSETVL PASS] [Committed,V2] RISC-V: Fix incorrect LCM delete bug [VSETVL PASS] - - - -1- 2024-01-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix incorrect LCM delete bug [VSETVL PASS] RISC-V: Fix incorrect LCM delete bug [VSETVL PASS] - - - -1- 2024-01-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add LCM delete block predecessors dump information RISC-V: Add LCM delete block predecessors dump information - - - -1- 2024-01-25 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove redundant full available computation [NFC] [Committed] RISC-V: Remove redundant full available computation [NFC] - - - -1- 2024-01-25 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add optim-no-fusion compile option [VSETVL PASS] [Committed] RISC-V: Add optim-no-fusion compile option [VSETVL PASS] - - - -1- 2024-01-25 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix large memory usage of VSETVL PASS [PR113495] RISC-V: Fix large memory usage of VSETVL PASS [PR113495] - - - -1- 2024-01-23 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix regressions due to 86de9b66480b710202a2898cf513db105d8c432f RISC-V: Fix regressions due to 86de9b66480b710202a2898cf513db105d8c432f - - - -1- 2024-01-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x RISC-V: Lower vmv.v.x (avl = 1) into vmv.s.x - - - -1- 2024-01-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes - - - -1- 2024-01-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Suppress warning [Committed] RISC-V: Suppress warning - - - -1- 2024-01-20 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix RVV_VLMAX [V2] RISC-V: Fix RVV_VLMAX - - - -1- 2024-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix RVV_VLMAX RISC-V: Fix RVV_VLMAX - - - -1- 2024-01-19 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support vi variant for vec_cmp RISC-V: Support vi variant for vec_cmp - - - -1- 2024-01-18 juzhe.zhong@rivai.ai Unresolved
[v2] test regression fix: Add !vect128 for variable length targets of bb-slp-subgroups-3.c [v2] test regression fix: Add !vect128 for variable length targets of bb-slp-subgroups-3.c - - - 1-- 2024-01-18 juzhe.zhong@rivai.ai Accepted
[Committed,V3] RISC-V: Add has compatible check for conflict vsetvl fusion [Committed,V3] RISC-V: Add has compatible check for conflict vsetvl fusion - - - -1- 2024-01-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Add has compatible check for conflict vsetvl fusion [V2] RISC-V: Add has compatible check for conflict vsetvl fusion - - - -1- 2024-01-17 juzhe.zhong@rivai.ai Unresolved
RISC-V: Add has compatible check for conflict vsetvl fusion RISC-V: Add has compatible check for conflict vsetvl fusion - - - -1- 2024-01-17 juzhe.zhong@rivai.ai Unresolved
[v2] test regression fix: Add vect128 for bb-slp-43.c [v2] test regression fix: Add vect128 for bb-slp-43.c - - - -1- 2024-01-16 juzhe.zhong@rivai.ai Unresolved
test regression fix: Remove xfail for variable length targets of bb-slp-subgroups-3.c test regression fix: Remove xfail for variable length targets of bb-slp-subgroups-3.c - - - 1-- 2024-01-16 juzhe.zhong@rivai.ai Accepted
test regression fix: Remove xfail for variable length targets test regression fix: Remove xfail for variable length targets - - - -1- 2024-01-16 juzhe.zhong@rivai.ai Unresolved
RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404] RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404] - - - -1- 2024-01-16 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro [Committed,V2] RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro - - - -1- 2024-01-15 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Adjust loop len by costing 1 when NITER < VF [Committed,V3] RISC-V: Adjust loop len by costing 1 when NITER < VF - - - -1- 2024-01-15 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add optimized dump check of VLS reduc tests [Committed] RISC-V: Add optimized dump check of VLS reduc tests - - - -1- 2024-01-15 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix attributes bug configuration of ternary instructions [Committed] RISC-V: Fix attributes bug configuration of ternary instructions - - - 1-- 2024-01-15 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro RISC-V: Fix regression (GCC-14 compare with GCC-13.2) of SHA256 from coremark-pro - - - -1- 2024-01-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Adjust loop len by costing 1 when NITER < VF RISC-V: Adjust loop len by costing 1 when NITER < VF - - - -1- 2024-01-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Adjust loop len by costing 1 when NITER < VF [GCC 14 regression] RISC-V: Adjust loop len by costing 1 when NITER < VF [GCC 14 regression] - - - -1- 2024-01-13 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Adjust scalar_to_vec cost [V3] RISC-V: Adjust scalar_to_vec cost - - - -1- 2024-01-12 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Enhance a testcase [Committed] RISC-V: Enhance a testcase - - - -1- 2024-01-12 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Adjust scalar_to_vec cost accurately [V2] RISC-V: Adjust scalar_to_vec cost accurately - - - -1- 2024-01-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: Increase scalar_to_vec_cost from 1 to 3 RISC-V: Increase scalar_to_vec_cost from 1 to 3 - - - -1- 2024-01-11 juzhe.zhong@rivai.ai Unresolved
RISC-V: VLA preempts VLS on unknown NITERS loop RISC-V: VLA preempts VLS on unknown NITERS loop - - - -1- 2024-01-11 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Switch RVV cost model. [V2] RISC-V: Switch RVV cost model. - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Switch RVV cost model to generic vector cost model RISC-V: Switch RVV cost model to generic vector cost model - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refine unsigned avg_floor/avg_ceil RISC-V: Refine unsigned avg_floor/avg_ceil - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Minor tweak dynamic cost model [V2] RISC-V: Minor tweak dynamic cost model - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
RISC-V: Minor tweak dynamic cost model RISC-V: Minor tweak dynamic cost model - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Robostify dynamic lmul test [Committed] RISC-V: Robostify dynamic lmul test - - - -1- 2024-01-10 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix comments of segment load/store intrinsic [Committed] RISC-V: Fix comments of segment load/store intrinsic - - - -1- 2024-01-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC] [Committed] RISC-V: Fix comments of segment load/store intrinsic[NFC] - - - 1-- 2024-01-09 juzhe.zhong@rivai.ai Accepted
RISC-V: Fix loop invariant check RISC-V: Fix loop invariant check - - - -1- 2024-01-09 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Use MAX instead of std::max [VSETVL PASS] [Committed] RISC-V: Use MAX instead of std::max [VSETVL PASS] - - - -1- 2024-01-07 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS] [Committed] RISC-V: Update MAX_SEW for available vsevl info[VSETVL PASS] - - - -1- 2024-01-06 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Teach liveness computation loop invariant shift amount [Committed,V2] RISC-V: Teach liveness computation loop invariant shift amount - - - -1- 2024-01-06 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move [Committed,V2] RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move - - - -1- 2024-01-06 juzhe.zhong@rivai.ai Unresolved
RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move RISC-V: Allow simplification non-vlmax with len = NUNITS reg to reg move - - - -1- 2024-01-05 juzhe.zhong@rivai.ai Unresolved
RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL] RISC-V: Teach liveness computation loop invariant shift amount[Dynamic LMUL] - - - -1- 2024-01-05 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Make liveness estimation be aware of .vi variant [Committed,V3] RISC-V: Make liveness estimation be aware of .vi variant - - - -1- 2024-01-04 juzhe.zhong@rivai.ai Unresolved
[Committed,V2] RISC-V: Make liveness estimation be aware of .vi variant [Committed,V2] RISC-V: Make liveness estimation be aware of .vi variant - - - -1- 2024-01-04 juzhe.zhong@rivai.ai Unresolved
RISC-V: Teach liveness estimation be aware of .vi variant RISC-V: Teach liveness estimation be aware of .vi variant - - - -1- 2024-01-04 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_STORE IFN [Committed] RISC-V: Refine LMUL computation for MASK_LEN_LOAD/MASK_LEN_STORE IFN - - - -1- 2024-01-04 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix indent [Committed] RISC-V: Fix indent - - - -1- 2024-01-03 juzhe.zhong@rivai.ai Unresolved
[Committed,V3] RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] [Committed,V3] RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] - - - -1- 2024-01-03 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] [V2] RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] - - - -1- 2024-01-03 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] RISC-V: Fix bug of earliest fusion for infinite loop[VSETVL PASS] - - - -1- 2024-01-03 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern [Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable [Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Robostify testcase pr113112-1.c [Committed] RISC-V: Robostify testcase pr113112-1.c - - - -1- 2023-12-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model - - - -1- 2023-12-29 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes [Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes - - - -1- 2023-12-28 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information [Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] [V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix typo [Committed] RISC-V: Fix typo - - - -1- 2023-12-26 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Some minior tweak on dynamic LMUL cost model [Committed] RISC-V: Some minior tweak on dynamic LMUL cost model - - - -1- 2023-12-26 juzhe.zhong@rivai.ai Unresolved
RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo RISC-V: Move RVV V_REGS liveness computation into analyze_loop_vinfo - - - -1- 2023-12-25 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add one more ASM check in PR113112-1.c [Committed] RISC-V: Add one more ASM check in PR113112-1.c - - - -1- 2023-12-25 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis [Committed] RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis - - - -1- 2023-12-22 juzhe.zhong@rivai.ai Unresolved
RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis RISC-V: Make PHI initial value occupy live V_REG in dynamic LMUL cost model analysis - - - -1- 2023-12-22 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Add dynamic LMUL test for x264 [Committed] RISC-V: Add dynamic LMUL test for x264 - - - 1-- 2023-12-21 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 syste… [Committed] RISC-V: Fix ICE of moving SUBREG of vector mode to DImode scalar register on RV32 syste… - - - -1- 2023-12-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF RISC-V: Optimize SELECT_VL codegen when length is known as smaller than VF - - - -1- 2023-12-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix bug of VSETVL fusion RISC-V: Fix bug of VSETVL fusion - - - -1- 2023-12-20 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
Regression FIX: Remove vect_variable_length XFAIL from some tests Regression FIX: Remove vect_variable_length XFAIL from some tests - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Refine some codes of expand_const_vector [NFC] [Committed] RISC-V: Refine some codes of expand_const_vector [NFC] - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Force scalable vector on all vsetvl tests [Committed] RISC-V: Force scalable vector on all vsetvl tests - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix FAIL of dynamic-lmul2-7.c [Committed] RISC-V: Fix FAIL of dynamic-lmul2-7.c - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove 256/512/1024 VLS vectors [Committed] RISC-V: Remove 256/512/1024 VLS vectors - - - -1- 2023-12-19 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Support one more overlap for wv instructions [V2] RISC-V: Support one more overlap for wv instructions - - - -1- 2023-12-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Support one more overlap for wv instructions RISC-V: Support one more overlap for wv instructions - - - -1- 2023-12-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Enable vect test for RV32 [V2] RISC-V: Enable vect test for RV32 - - - -1- 2023-12-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Enable vect test for RV32 RISC-V: Enable vect test for RV32 - - - -1- 2023-12-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix natural regsize for fixed-vlmax of -march=rv64gc_zve32f RISC-V: Fix natural regsize for fixed-vlmax of -march=rv64gc_zve32f - - - -1- 2023-12-18 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Fix vmerge optimization bug in vec_perm vectorization [V2] RISC-V: Fix vmerge optimization bug in vec_perm vectorization - - - -1- 2023-12-15 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Remove xfail for some of the SLP tests [Committed] RISC-V: Remove xfail for some of the SLP tests - - - -1- 2023-12-15 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix vmerge optimization bug in vec_perm vectorization RISC-V: Fix vmerge optimization bug in vec_perm vectorization - - - -1- 2023-12-15 juzhe.zhong@rivai.ai Unresolved
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