Show patches with: Series = RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations       |   1 patch
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations - - - 1-- 2023-06-01 juzhe.zhong@rivai.ai Accepted